hwaddr cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr) { uint32_t paddr; uint32_t page_size; unsigned access; if (xtensa_get_physical_addr(env, false, addr, 0, 0, &paddr, &page_size, &access) == 0) { return paddr; } if (xtensa_get_physical_addr(env, false, addr, 2, 0, &paddr, &page_size, &access) == 0) { return paddr; } return ~0; }
void tlb_fill(CPUXtensaState *env1, target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) { CPUXtensaState *saved_env = env; env = env1; { uint32_t paddr; uint32_t page_size; unsigned access; int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx, &paddr, &page_size, &access); qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__, vaddr, is_write, mmu_idx, paddr, ret); if (ret == 0) { tlb_set_page(env, vaddr & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); } else { do_restore_state(retaddr); HELPER(exception_cause_vaddr)(env->pc, ret, vaddr); } } env = saved_env; }
static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) { uint32_t paddr; uint32_t page_size; unsigned access; int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, &paddr, &page_size, &access); if (ret == 0) { tb_invalidate_phys_addr(paddr); } }
void tlb_fill(CPUState *cs, target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; uint32_t paddr; uint32_t page_size; unsigned access; int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx, &paddr, &page_size, &access); qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__, vaddr, is_write, mmu_idx, paddr, ret); if (ret == 0) { tlb_set_page(cs, vaddr & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); } else { cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } }