void tms34061_device::write(address_space &space, int col, int row, int func, UINT8 data)
{
offs_t offs;
/* the function code determines what to do */
switch (func)
{
/* both 0 and 2 map to register access */
case 0:
case 2:
register_w(space, col, data);
break;
/* function 1 maps to XY access; col is the address adjustment */
case 1:
xypixel_w(space, col, data);
break;
/* function 3 maps to direct access */
case 3:
offs = ((row << m_rowshift) | col) & m_vrammask;
if (m_regs[TMS34061_CONTROL2] & 0x0040)
offs |= (m_regs[TMS34061_CONTROL2] & 3) << 16;
if (VERBOSE) logerror("%s:tms34061 direct (%04x) = %02x/%02x\n", space.machine().describe_context(), offs, data, m_latchdata);
if (m_vram[offs] != data || m_latchram[offs] != m_latchdata)
{
m_vram[offs] = data;
m_latchram[offs] = m_latchdata;
}
break;
/* function 4 performs a shift reg transfer to VRAM */
case 4:
offs = col << m_rowshift;
if (m_regs[TMS34061_CONTROL2] & 0x0040)
offs |= (m_regs[TMS34061_CONTROL2] & 3) << 16;
offs &= m_vrammask;
if (VERBOSE) logerror("%s:tms34061 shiftreg write (%04x)\n", space.machine().describe_context(), offs);
memcpy(&m_vram[offs], m_shiftreg, (size_t)1 << m_rowshift);
memset(&m_latchram[offs], m_latchdata, (size_t)1 << m_rowshift);
break;
/* function 5 performs a shift reg transfer from VRAM */
case 5:
offs = col << m_rowshift;
if (m_regs[TMS34061_CONTROL2] & 0x0040)
offs |= (m_regs[TMS34061_CONTROL2] & 3) << 16;
offs &= m_vrammask;
if (VERBOSE) logerror("%s:tms34061 shiftreg read (%04x)\n", space.machine().describe_context(), offs);
m_shiftreg = &m_vram[offs];
break;
/* log anything else */
default:
logerror("%s:Unsupported TMS34061 function %d\n", space.machine().describe_context(), func);
break;
}
}
void tms34061_w(int col, int row, int func, UINT8 data)
{
offs_t offs;
/* the function code determines what to do */
switch (func)
{
/* both 0 and 2 map to register access */
case 0:
case 2:
register_w(col, data);
break;
/* function 1 maps to XY access; col is the address adjustment */
case 1:
xypixel_w(col, data);
break;
/* function 3 maps to direct access */
case 3:
offs = ((row << tms34061.intf.rowshift) | col) & tms34061.vrammask;
if (tms34061.regs[TMS34061_CONTROL2] & 0x0040)
offs |= (tms34061.regs[TMS34061_CONTROL2] & 3) << 16;
if (tms34061.vram[offs] != data || tms34061.latchram[offs] != tms34061.latchdata)
{
tms34061.vram[offs] = data;
tms34061.latchram[offs] = tms34061.latchdata;
}
break;
/* function 4 performs a shift reg transfer to VRAM */
case 4:
offs = col << tms34061.intf.rowshift;
if (tms34061.regs[TMS34061_CONTROL2] & 0x0040)
offs |= (tms34061.regs[TMS34061_CONTROL2] & 3) << 16;
offs &= tms34061.vrammask;
memcpy(&tms34061.vram[offs], tms34061.shiftreg, (size_t)1 << tms34061.intf.rowshift);
memset(&tms34061.latchram[offs], tms34061.latchdata, (size_t)1 << tms34061.intf.rowshift);
break;
/* function 5 performs a shift reg transfer from VRAM */
case 5:
offs = col << tms34061.intf.rowshift;
if (tms34061.regs[TMS34061_CONTROL2] & 0x0040)
offs |= (tms34061.regs[TMS34061_CONTROL2] & 3) << 16;
offs &= tms34061.vrammask;
tms34061.shiftreg = &tms34061.vram[offs];
break;
/* log anything else */
default:
logerror("Unsupported TMS34061 function %d - PC: %04X\n", func, activecpu_get_pc());
break;
}
}
