static void emit_wrapper(struct function *f, struct cu *cu)
{
struct parameter *parm;
const char *name = function__name(f, cu);
int regparm = 0, needs_wrapper = 0;
function__for_each_parameter(f, parm) {
const uint16_t type_id = parm->tag.type;
struct tag *type = cu__type(cu, type_id);
tag__assert_search_result(type);
if (type->tag == DW_TAG_base_type) {
struct base_type *bt = tag__base_type(type);
char bf[64];
if (bt->bit_size < 64 &&
strncmp(base_type__name(bt, cu, bf, sizeof(bf)),
"unsigned", 8) == 0) {
if (!needs_wrapper) {
printf("wrap_%s:\n", name);
needs_wrapper = 1;
}
zero_extend(regparm, bt, cu,
parameter__name(parm, cu));
}
}
++regparm;
}
if (needs_wrapper)
printf("\tj\t%s\n\n", name);
}
static void dec_xor(DisasContext *dc)
{
if (dc->format == OP_FMT_RI) {
LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
zero_extend(dc->imm16, 16));
} else {
LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
if (dc->format == OP_FMT_RI) {
tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
zero_extend(dc->imm16, 16));
} else {
tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
}
}
static void dec_nor(DisasContext *dc)
{
if (dc->format == OP_FMT_RI) {
LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
zero_extend(dc->imm16, 16));
} else {
LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
if (dc->format == OP_FMT_RI) {
TCGv t0 = tcg_temp_new();
tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0);
tcg_temp_free(t0);
} else {
tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
}
}
static void dec_cmpgu(DisasContext *dc)
{
if (dc->format == OP_FMT_RI) {
LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
zero_extend(dc->imm16, 16));
} else {
LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
gen_compare(dc, TCG_COND_GTU);
}
static void dec_and(DisasContext *dc)
{
if (dc->format == OP_FMT_RI) {
LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
zero_extend(dc->imm16, 16));
} else {
LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
if (dc->format == OP_FMT_RI) {
tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
zero_extend(dc->imm16, 16));
} else {
if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
gen_helper_hlt(cpu_env);
} else {
tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
}
}
}
static inline void gen_compare(DisasContext *dc, int cond)
{
int i;
if (dc->format == OP_FMT_RI) {
switch (cond) {
case TCG_COND_GEU:
case TCG_COND_GTU:
i = zero_extend(dc->imm16, 16);
break;
default:
i = sign_extend(dc->imm16, 16);
break;
}
tcg_gen_setcondi_tl(cond, cpu_R[dc->r1], cpu_R[dc->r0], i);
} else {
tcg_gen_setcond_tl(cond, cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
}
}
void armv7a::arm_mov_imm(armv7a_ir& inst)
{
inst.print_inst("arm_mov_imm");
if(rf.condition_passed(inst.cond()))
{
bits imm32(0, 32);
bool setflags;
uint32_t d;
uint32_t carry;
//Encoding A1
if(inst(21) == 1)
{
inst.check(27, 21, B(001 1101));
uint32_t s = inst(20);
uint32_t rd = inst(15, 12);
bits imm12(inst(11, 0), 12);
if((rd == B(1111)) && (s == 1))
{
printb(d_inst_dpmisc, "arm_mov_imm SUBS PC, LR");
}
d = rd;
setflags = s == 1;
arm_expand_imm_c(&imm32, &carry, imm12, rf.cpsr_C());
}
//Encoding A2
else
{
inst.check(27, 20, B(0011 0000));
uint32_t rd = inst(15, 12);
bits imm4_12((inst(19, 16) << 12) | inst(11, 0), 16);
d = rd;
setflags = false;
zero_extend(&imm32, imm4_12, 32);
if(d == 15)
{
printb(d_inst, "arm_mov_imm unpredictable");
}
}
//ESO
bits result(imm32.val, 32);
if(d == 15)
{
printd(d_inst, "mov_imm d == 15");
rf.alu_write_pc(result.val);
}
else
{
printd(d_inst, "mov_imm d != 15");
rf.r_write(d, result.val);
if(setflags)
{
rf.cpsr_N(result(31));
rf.cpsr_Z(is_zero_bit(result));
rf.cpsr_C(carry);
}
}
}
}
