int ps7_init(void) { int ret; // MIO init ret = zynq_mio_init(); if (ret != PS7_INIT_SUCCESS) return ret; // PLL init ret = zynq_pll_init(); if (ret != PS7_INIT_SUCCESS) return ret; // Clock init ret = zynq_clk_init(); if (ret != PS7_INIT_SUCCESS) return ret; // DDR init ret = ps7_config (ps7_ddr_init_data_3_0); if (ret != PS7_INIT_SUCCESS) return ret; // Peripherals init ret = ps7_config (ps7_peripherals_init_data_3_0); if (ret != PS7_INIT_SUCCESS) return ret; // post config ret = ps7_config (ps7_post_config_3_0); if (ret != PS7_INIT_SUCCESS) return ret; return PS7_INIT_SUCCESS; }
void platform_early_init(void) { zynq_mio_init(); zynq_pll_init(); zynq_clk_init(); #if ZYNQ_SDRAM_INIT zynq_ddr_init(); #endif zynq_slcr_unlock(); /* Enable all level shifters */ SLCR_REG(LVL_SHFTR_EN) = 0xF; /* FPGA SW reset (not documented, but mandatory) */ SLCR_REG(FPGA_RST_CTRL) = 0x0; /* zynq manual says this is mandatory for cache init */ *REG32(SLCR_BASE + 0xa1c) = 0x020202; zynq_slcr_lock(); /* early initialize the uart so we can printf */ uart_init_early(); /* initialize the interrupt controller */ arm_gic_init(); /* initialize the timer block */ arm_cortex_a9_timer_init(CPUPRIV_BASE, zynq_get_arm_timer_freq()); /* add the main memory arena */ #if !ZYNQ_CODE_IN_SDRAM && SDRAM_SIZE != 0 /* In the case of running from SRAM, and we are using SDRAM, * there is a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB), * so intentionally bump the boot-time allocator to start in the base of SDRAM. */ extern uintptr_t boot_alloc_start; extern uintptr_t boot_alloc_end; boot_alloc_start = KERNEL_BASE + MB; boot_alloc_end = KERNEL_BASE + MB; #endif #if SDRAM_SIZE != 0 pmm_add_arena(&sdram_arena); #endif pmm_add_arena(&sram_arena); }
void platform_early_init(void) { #if 0 ps7_init(); #else /* Unlock the registers and leave them that way */ zynq_slcr_unlock(); zynq_mio_init(); zynq_pll_init(); zynq_clk_init(); #if ZYNQ_SDRAM_INIT zynq_ddr_init(); #endif #endif /* Enable all level shifters */ SLCR_REG(LVL_SHFTR_EN) = 0xF; /* FPGA SW reset (not documented, but mandatory) */ SLCR_REG(FPGA_RST_CTRL) = 0x0; /* zynq manual says this is mandatory for cache init */ *REG32(SLCR_BASE + 0xa1c) = 0x020202; /* early initialize the uart so we can printf */ uart_init_early(); /* initialize the interrupt controller */ arm_gic_init(); zynq_gpio_init(); /* initialize the timer block */ arm_cortex_a9_timer_init(CPUPRIV_BASE, zynq_get_arm_timer_freq()); /* bump the 2nd cpu into our code space and remap the top SRAM block */ if (KERNEL_LOAD_OFFSET != 0) { /* construct a trampoline to get the 2nd cpu up to the trap routine */ /* figure out the offset of the trampoline routine in physical space from address 0 */ extern void platform_reset(void); addr_t tramp = (addr_t)&platform_reset; tramp -= KERNEL_BASE; tramp += MEMBASE; /* stuff in a ldr pc, [nextaddrress], and a target address */ uint32_t *ptr = (uint32_t *)KERNEL_BASE; ptr[0] = 0xe51ff004; // ldr pc, [pc, #-4] ptr[1] = tramp; arch_clean_invalidate_cache_range((addr_t)ptr, 8); } /* reset the 2nd cpu, letting it go through its reset vector (at 0x0 physical) */ SLCR_REG(A9_CPU_RST_CTRL) |= (1<<1); // reset cpu 1 spin(10); SLCR_REG(A9_CPU_RST_CTRL) &= ~(1<<1); // unreset cpu 1 /* wait for the 2nd cpu to reset, go through the usual reset vector, and get trapped by our code */ /* see platform/zynq/reset.S */ extern volatile int __cpu_trapped; uint count = 100000; while (--count) { arch_clean_invalidate_cache_range((addr_t)&__cpu_trapped, sizeof(__cpu_trapped)); if (__cpu_trapped != 0) break; } if (count == 0) { panic("ZYNQ: failed to trap 2nd cpu\n"); } /* bounce the 4th sram region down to lower address */ SLCR_REG(OCM_CFG) &= ~0xf; /* all banks at low address */ /* add the main memory arena */ #if !ZYNQ_CODE_IN_SDRAM && SDRAM_SIZE != 0 /* In the case of running from SRAM, and we are using SDRAM, * there is a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB), * so intentionally bump the boot-time allocator to start in the base of SDRAM. */ extern uintptr_t boot_alloc_start; extern uintptr_t boot_alloc_end; boot_alloc_start = KERNEL_BASE + MB; boot_alloc_end = KERNEL_BASE + MB; #endif #if SDRAM_SIZE != 0 pmm_add_arena(&sdram_arena); #endif pmm_add_arena(&sram_arena); }