int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
unsigned long ts; /* Timestamp */
u32 partialbit = 0;
u32 i, control, isr_status, status, swap, diff;
u32 *buf_start;
/* Detect if we are going working with partial or full bitstream */
if (bsize != desc->size) {
printf("%s: Working with partial bitstream\n", __func__);
partialbit = 1;
}
buf_start = check_data((u8 *)buf, bsize, &swap);
if (!buf_start)
return FPGA_FAIL;
/* Check if data is postpone from start */
diff = (u32)buf_start - (u32)buf;
if (diff) {
printf("%s: Bitstream is not validated yet (diff %x)\n",
__func__, diff);
return FPGA_FAIL;
}
if ((u32)buf_start & 0x3) {
u32 *new_buf = (u32 *)((u32)buf & ~0x3);
printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
(u32)buf_start, (u32)new_buf, swap);
for (i = 0; i < (bsize/4); i++)
new_buf[i] = load_word(&buf_start[i], swap);
swap = SWAP_DONE;
buf = new_buf;
} else if (swap != SWAP_DONE) {
/* For bitstream which are aligned */
u32 *new_buf = (u32 *)buf;
printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
swap);
for (i = 0; i < (bsize/4); i++)
new_buf[i] = load_word(&buf_start[i], swap);
swap = SWAP_DONE;
}
/* Clear loopback bit */
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
if (!partialbit) {
zynq_slcr_devcfg_disable();
/* Setting PCFG_PROG_B signal to high */
control = readl(&devcfg_base->ctrl);
writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
/* Setting PCFG_PROG_B signal to low */
writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
/* Polling the PCAP_INIT status for Reset */
ts = get_timer(0);
while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for INIT to clear\n",
__func__);
return FPGA_FAIL;
}
}
/* Setting PCFG_PROG_B signal to high */
writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
/* Polling the PCAP_INIT status for Set */
ts = get_timer(0);
while (!(readl(&devcfg_base->status) &
DEVCFG_STATUS_PCFG_INIT)) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for INIT to set\n",
__func__);
return FPGA_FAIL;
}
}
}
isr_status = readl(&devcfg_base->int_sts);
/* Clear it all, so if Boot ROM comes back, it can proceed */
writel(0xFFFFFFFF, &devcfg_base->int_sts);
if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
/* If RX FIFO overflow, need to flush RX FIFO first */
if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
writel(0xFFFFFFFF, &devcfg_base->int_sts);
}
return FPGA_FAIL;
}
status = readl(&devcfg_base->status);
debug("%s: Status = 0x%08X\n", __func__, status);
if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
debug("%s: Error: device busy\n", __func__);
return FPGA_FAIL;
}
debug("%s: Device ready\n", __func__);
if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
/* Error state, transfer cannot occur */
debug("%s: ISR indicates error\n", __func__);
return FPGA_FAIL;
} else {
/* Clear out the status */
writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
}
}
if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
/* Clear the count of completed DMA transfers */
writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
}
debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
debug("%s: Size = %zu\n", __func__, bsize);
/* Set up the transfer */
writel((u32)buf | 1, &devcfg_base->dma_src_addr);
writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
writel(bsize >> 2, &devcfg_base->dma_src_len);
writel(0, &devcfg_base->dma_dst_len);
isr_status = readl(&devcfg_base->int_sts);
/* Polling the PCAP_INIT status for Set */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
debug("%s: Error: isr = 0x%08X\n", __func__,
isr_status);
debug("%s: Write count = 0x%08X\n", __func__,
readl(&devcfg_base->write_count));
debug("%s: Read count = 0x%08X\n", __func__,
readl(&devcfg_base->read_count));
return FPGA_FAIL;
}
if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
printf("%s: Timeout wait for DMA to complete\n",
__func__);
return FPGA_FAIL;
}
isr_status = readl(&devcfg_base->int_sts);
}
debug("%s: DMA transfer is done\n", __func__);
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
}
isr_status = readl(&devcfg_base->int_sts);
}
debug("%s: FPGA config done\n", __func__);
/* Clear out the DMA status */
writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
if (!partialbit)
zynq_slcr_devcfg_enable();
return FPGA_SUCCESS;
}
int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
unsigned long ts; /* Timestamp */
u32 control;
u32 isr_status;
u32 status;
const u32 *test = buf;
int i;
/* Check bitstream size */
if (bsize != desc->size) {
printf("Error: File size is wrong - should be %x.\n",
desc->size);
return FPGA_FAIL;
}
/* Checking that passing bin is not a bitstream */
for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
if (test[i] != bin_format[i]) {
puts("Error: File not in binary format.\n");
return FPGA_FAIL;
}
}
zynq_slcr_devcfg_disable();
/* Setting PCFG_PROG_B signal to high */
control = readl(&devcfg_base->ctrl);
writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
/* Setting PCFG_PROG_B signal to low */
writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
/* Polling the PCAP_INIT status for Reset */
ts = get_timer(0);
while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
puts("Error: Timeout waiting for INIT to clear.\n");
return FPGA_FAIL;
}
}
/* Setting PCFG_PROG_B signal to high */
writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
/* Polling the PCAP_INIT status for Set */
ts = get_timer(0);
while (!(readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT)) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
puts("Error: Timeout waiting for INIT to set.\n");
return FPGA_FAIL;
}
}
isr_status = readl(&devcfg_base->int_sts);
/* Clear it all, so if Boot ROM comes back, it can proceed */
writel(0xFFFFFFFF, &devcfg_base->int_sts);
if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
debug("Fatal errors in PCAP 0x%X\n", isr_status);
/* If RX FIFO overflow, need to flush RX FIFO first */
if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
writel(0xFFFFFFFF, &devcfg_base->int_sts);
}
return FPGA_FAIL;
}
status = readl(&devcfg_base->status);
debug("status = 0x%08X\n", status);
if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
debug("Error: device busy\n");
return FPGA_FAIL;
}
debug("device ready\n");
if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
/* Error state, transfer cannot occur */
debug("isr indicates error\n");
return FPGA_FAIL;
} else {
/* Clear out the status */
writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
}
}
if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
/* Clear the count of completed DMA transfers */
writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
}
debug("Source = 0x%08X\n", (u32)buf);
debug("Size = %zu\n", bsize);
/* Set up the transfer */
writel((u32)buf | 1, &devcfg_base->dma_src_addr);
writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
writel(bsize >> 2, &devcfg_base->dma_src_len);
writel(0, &devcfg_base->dma_dst_len);
isr_status = readl(&devcfg_base->int_sts);
/* Polling the PCAP_INIT status for Set */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
debug("Error: isr = 0x%08X\n", isr_status);
debug("Write count = 0x%08X\n",
readl(&devcfg_base->write_count));
debug("Read count = 0x%08X\n",
readl(&devcfg_base->read_count));
return FPGA_FAIL;
}
if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
puts("Error: Timeout waiting for DMA to complete.\n");
return FPGA_FAIL;
}
isr_status = readl(&devcfg_base->int_sts);
}
debug("DMA transfer is done\n");
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
puts("Error: Timeout waiting for FPGA to config.\n");
return FPGA_FAIL;
}
isr_status = readl(&devcfg_base->int_sts);
}
debug("FPGA config done\n");
/* Clear out the DMA status */
writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
zynq_slcr_devcfg_enable();
return FPGA_SUCCESS;
}
