int board_init(void) { #ifdef CONFIG_FPGA u32 idcode; idcode = zynq_slcr_get_idcode(); switch (idcode) { case XILINX_ZYNQ_7010: fpga = fpga010; break; case XILINX_ZYNQ_7020: fpga = fpga020; break; case XILINX_ZYNQ_7030: fpga = fpga030; break; case XILINX_ZYNQ_7045: fpga = fpga045; break; } #endif icache_enable(); #ifdef CONFIG_FPGA fpga_init(); fpga_add(fpga_xilinx, &fpga); #endif return 0; }
int board_init(void) { #if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD) unsigned char eepromsel = CONFIG_SYS_I2C_MUX_EEPROM_SEL; #endif #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) u32 idcode; idcode = zynq_slcr_get_idcode(); switch (idcode) { case XILINX_ZYNQ_7010: fpga = fpga010; break; case XILINX_ZYNQ_7015: fpga = fpga015; break; case XILINX_ZYNQ_7020: fpga = fpga020; break; case XILINX_ZYNQ_7030: fpga = fpga030; break; case XILINX_ZYNQ_7035: fpga = fpga035; break; case XILINX_ZYNQ_7045: fpga = fpga045; break; case XILINX_ZYNQ_7100: fpga = fpga100; break; } #endif #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); fpga_add(fpga_xilinx, &fpga); #endif #if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD) if (eeprom_write(CONFIG_SYS_I2C_MUX_ADDR, 0, &eepromsel, 1)) puts("I2C:EEPROM selection failed\n"); #endif /* Added by MYIR for MYS-XC7Z010 */ myir_board_init(); return 0; }
int board_init(void) { #if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD) unsigned char eepromsel = CONFIG_SYS_I2C_MUX_EEPROM_SEL; #endif #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) u32 idcode; idcode = zynq_slcr_get_idcode(); switch (idcode) { case XILINX_ZYNQ_7010: fpga = fpga010; break; case XILINX_ZYNQ_7015: fpga = fpga015; break; case XILINX_ZYNQ_7020: fpga = fpga020; break; case XILINX_ZYNQ_7030: fpga = fpga030; break; case XILINX_ZYNQ_7045: fpga = fpga045; break; case XILINX_ZYNQ_7100: fpga = fpga100; break; } #endif /* * temporary hack to clear pending irqs before Linux as it * will hang Linux */ writel(0x26d, 0xe0001014); #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); fpga_add(fpga_xilinx, &fpga); #endif #if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD) if (eeprom_write(CONFIG_SYS_I2C_MUX_ADDR, 0, &eepromsel, 1)) puts("I2C:EEPROM selection failed\n"); #endif return 0; }
int board_init(void) { #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) u32 idcode; idcode = zynq_slcr_get_idcode(); switch (idcode) { case XILINX_ZYNQ_7007S: fpga = fpga007s; break; case XILINX_ZYNQ_7010: fpga = fpga010; break; case XILINX_ZYNQ_7012S: fpga = fpga012s; break; case XILINX_ZYNQ_7014S: fpga = fpga014s; break; case XILINX_ZYNQ_7015: fpga = fpga015; break; case XILINX_ZYNQ_7020: fpga = fpga020; break; case XILINX_ZYNQ_7030: fpga = fpga030; break; case XILINX_ZYNQ_7035: fpga = fpga035; break; case XILINX_ZYNQ_7045: fpga = fpga045; break; case XILINX_ZYNQ_7100: fpga = fpga100; break; } #endif #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); fpga_add(fpga_xilinx, &fpga); #endif return 0; }
int board_init(void) { #ifdef CONFIG_FPGA u32 idcode; idcode = zynq_slcr_get_idcode(); switch (idcode) { case XILINX_ZYNQ_7010: fpga = fpga010; break; case XILINX_ZYNQ_7020: fpga = fpga020; break; case XILINX_ZYNQ_7030: fpga = fpga030; break; case XILINX_ZYNQ_7045: fpga = fpga045; break; case XILINX_ZYNQ_7100: fpga = fpga100; break; } #endif /* temporary hack to clear pending irqs before Linux as it * will hang Linux */ writel(0x26d, 0xe0001014); /* temporary hack to take USB out of reset til the is fixed * in Linux */ writel(0x80, 0xe000a204); writel(0x80, 0xe000a208); writel(0x80, 0xe000a040); writel(0x00, 0xe000a040); writel(0x80, 0xe000a040); // icache_enable(); #ifdef CONFIG_FPGA fpga_init(); fpga_add(fpga_xilinx, &fpga); #endif return 0; }