void CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const { assert(SubRegsComplete && "Must precompute sub-registers"); std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices"); for (unsigned i = 0, e = Indices.size(); i != e; ++i) { CodeGenRegister *SR = SubRegs.find(Indices[i])->second; if (OSet.insert(SR)) SR->addSubRegsPreOrder(OSet); } }
// Compute sets of overlapping registers. // // The standard set is all super-registers and all sub-registers, but the // target description can add arbitrary overlapping registers via the 'Aliases' // field. This complicates things, but we can compute overlapping sets using // the following rules: // // 1. The relation overlap(A, B) is reflexive and symmetric but not transitive. // // 2. overlap(A, B) implies overlap(A, S) for all S in supers(B). // // Alternatively: // // overlap(A, B) iff there exists: // A' in { A, subregs(A) } and B' in { B, subregs(B) } such that: // A' = B' or A' in aliases(B') or B' in aliases(A'). // // Here subregs(A) is the full flattened sub-register set returned by // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the // description of register A. // // This also implies that registers with a common sub-register are considered // overlapping. This can happen when forming register pairs: // // P0 = (R0, R1) // P1 = (R1, R2) // P2 = (R2, R3) // // In this case, we will infer an overlap between P0 and P1 because of the // shared sub-register R1. There is no overlap between P0 and P2. // void CodeGenRegBank:: computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) { assert(Map.empty()); // Collect overlaps that don't follow from rule 2. for (unsigned i = 0, e = Registers.size(); i != e; ++i) { CodeGenRegister *Reg = Registers[i]; CodeGenRegister::Set &Overlaps = Map[Reg]; // Reg overlaps itself. Overlaps.insert(Reg); // All super-registers overlap. const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs(); Overlaps.insert(Supers.begin(), Supers.end()); // Form symmetrical relations from the special Aliases[] lists. std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases"); for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) { CodeGenRegister *Reg2 = getReg(RegList[i2]); CodeGenRegister::Set &Overlaps2 = Map[Reg2]; const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs(); // Reg overlaps Reg2 which implies it overlaps supers(Reg2). Overlaps.insert(Reg2); Overlaps.insert(Supers2.begin(), Supers2.end()); Overlaps2.insert(Reg); Overlaps2.insert(Supers.begin(), Supers.end()); } } // Apply rule 2. and inherit all sub-register overlaps. for (unsigned i = 0, e = Registers.size(); i != e; ++i) { CodeGenRegister *Reg = Registers[i]; CodeGenRegister::Set &Overlaps = Map[Reg]; const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(), e2 = SRM.end(); i2 != e2; ++i2) { CodeGenRegister::Set &Overlaps2 = Map[i2->second]; Overlaps.insert(Overlaps2.begin(), Overlaps2.end()); } } }
BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { SetVector<const CodeGenRegister*> Set; // First add Regs with all sub-registers. for (unsigned i = 0, e = Regs.size(); i != e; ++i) { CodeGenRegister *Reg = getReg(Regs[i]); if (Set.insert(Reg)) // Reg is new, add all sub-registers. // The pre-ordering is not important here. Reg->addSubRegsPreOrder(Set, *this); } // Second, find all super-registers that are completely covered by the set. for (unsigned i = 0; i != Set.size(); ++i) { const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs(); for (unsigned j = 0, e = SR.size(); j != e; ++j) { const CodeGenRegister *Super = SR[j]; if (!Super->CoveredBySubRegs || Set.count(Super)) continue; // This new super-register is covered by its sub-registers. bool AllSubsInSet = true; const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(), E = SRM.end(); I != E; ++I) if (!Set.count(I->second)) { AllSubsInSet = false; break; } // All sub-registers in Set, add Super as well. // We will visit Super later to recheck its super-registers. if (AllSubsInSet) Set.insert(Super); } } // Convert to BitVector. BitVector BV(Registers.size() + 1); for (unsigned i = 0, e = Set.size(); i != e; ++i) BV.set(Set[i]->EnumValue); return BV; }
const CodeGenRegister::SubRegMap & CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) { // Only compute this map once. if (SubRegsComplete) return SubRegs; SubRegsComplete = true; std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs"); std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices"); if (SubList.size() != Indices.size()) throw TGError(TheDef->getLoc(), "Register " + getName() + " SubRegIndices doesn't match SubRegs"); // First insert the direct subregs and make sure they are fully indexed. for (unsigned i = 0, e = SubList.size(); i != e; ++i) { CodeGenRegister *SR = RegBank.getReg(SubList[i]); if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second) throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() + " appears twice in Register " + getName()); } // Keep track of inherited subregs and how they can be reached. SmallVector<Orphan, 8> Orphans; // Clone inherited subregs and place duplicate entries on Orphans. // Here the order is important - earlier subregs take precedence. for (unsigned i = 0, e = SubList.size(); i != e; ++i) { CodeGenRegister *SR = RegBank.getReg(SubList[i]); const SubRegMap &Map = SR->getSubRegs(RegBank); // Add this as a super-register of SR now all sub-registers are in the list. // This creates a topological ordering, the exact order depends on the // order getSubRegs is called on all registers. SR->SuperRegs.push_back(this); for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE; ++SI) { if (!SubRegs.insert(*SI).second) Orphans.push_back(Orphan(SI->second, Indices[i], SI->first)); // Noop sub-register indexes are possible, so avoid duplicates. if (SI->second != SR) SI->second->SuperRegs.push_back(this); } } // Process the composites. ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices"); for (unsigned i = 0, e = Comps->size(); i != e; ++i) { DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i)); if (!Pat) throw TGError(TheDef->getLoc(), "Invalid dag '" + Comps->getElement(i)->getAsString() + "' in CompositeIndices"); DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator()); if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex")) throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " + Pat->getAsString()); // Resolve list of subreg indices into R2. CodeGenRegister *R2 = this; for (DagInit::const_arg_iterator di = Pat->arg_begin(), de = Pat->arg_end(); di != de; ++di) { DefInit *IdxInit = dynamic_cast<DefInit*>(*di); if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex")) throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " + Pat->getAsString()); const SubRegMap &R2Subs = R2->getSubRegs(RegBank); SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef()); if (ni == R2Subs.end()) throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() + " refers to bad index in " + R2->getName()); R2 = ni->second; } // Insert composite index. Allow overriding inherited indices etc. SubRegs[BaseIdxInit->getDef()] = R2; // R2 is no longer an orphan. for (unsigned j = 0, je = Orphans.size(); j != je; ++j) if (Orphans[j].SubReg == R2) Orphans[j].SubReg = 0; } // Now Orphans contains the inherited subregisters without a direct index. // Create inferred indexes for all missing entries. for (unsigned i = 0, e = Orphans.size(); i != e; ++i) { Orphan &O = Orphans[i]; if (!O.SubReg) continue; SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] = O.SubReg; } return SubRegs; }
CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) : TheDef(R), Name(R->getName()), EnumValue(-1) { // Rename anonymous register classes. if (R->getName().size() > 9 && R->getName()[9] == '.') { static unsigned AnonCounter = 0; R->setName("AnonRegClass_"+utostr(AnonCounter++)); } std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { Record *Type = TypeList[i]; if (!Type->isSubClassOf("ValueType")) throw "RegTypes list member '" + Type->getName() + "' does not derive from the ValueType class!"; VTs.push_back(getValueType(Type)); } assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); // Allocation order 0 is the full set. AltOrders provides others. const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); ListInit *AltOrders = R->getValueAsListInit("AltOrders"); Orders.resize(1 + AltOrders->size()); // Default allocation order always contains all registers. for (unsigned i = 0, e = Elements->size(); i != e; ++i) { Orders[0].push_back((*Elements)[i]); Members.insert(RegBank.getReg((*Elements)[i])); } // Alternative allocation orders may be subsets. SetTheory::RecSet Order; for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { RegBank.getSets().evaluate(AltOrders->getElement(i), Order); Orders[1 + i].append(Order.begin(), Order.end()); // Verify that all altorder members are regclass members. while (!Order.empty()) { CodeGenRegister *Reg = RegBank.getReg(Order.back()); Order.pop_back(); if (!contains(Reg)) throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() + " is not a class member"); } } // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags. ListInit *SRC = R->getValueAsListInit("SubRegClasses"); for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) { DagInit *DAG = dynamic_cast<DagInit*>(*i); if (!DAG) throw "SubRegClasses must contain DAGs"; DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator()); Record *RCRec; if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass")) throw "Operator '" + DAG->getOperator()->getAsString() + "' in SubRegClasses is not a RegisterClass"; // Iterate over args, all SubRegIndex instances. for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end(); ai != ae; ++ai) { DefInit *Idx = dynamic_cast<DefInit*>(*ai); Record *IdxRec; if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex")) throw "Argument '" + (*ai)->getAsString() + "' in SubRegClasses is not a SubRegIndex"; if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second) throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice"; } } // Allow targets to override the size in bits of the RegisterClass. unsigned Size = R->getValueAsInt("Size"); Namespace = R->getValueAsString("Namespace"); SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits(); SpillAlignment = R->getValueAsInt("Alignment"); CopyCost = R->getValueAsInt("CopyCost"); Allocatable = R->getValueAsBit("isAllocatable"); AltOrderSelect = R->getValueAsCode("AltOrderSelect"); }
const CodeGenRegister::SubRegMap & CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) { // Only compute this map once. if (SubRegsComplete) return SubRegs; SubRegsComplete = true; std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs"); std::vector<Record*> IdxList = TheDef->getValueAsListOfDefs("SubRegIndices"); if (SubList.size() != IdxList.size()) throw TGError(TheDef->getLoc(), "Register " + getName() + " SubRegIndices doesn't match SubRegs"); // First insert the direct subregs and make sure they are fully indexed. SmallVector<CodeGenSubRegIndex*, 8> Indices; for (unsigned i = 0, e = SubList.size(); i != e; ++i) { CodeGenRegister *SR = RegBank.getReg(SubList[i]); CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(IdxList[i]); Indices.push_back(Idx); if (!SubRegs.insert(std::make_pair(Idx, SR)).second) throw TGError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() + " appears twice in Register " + getName()); } // Keep track of inherited subregs and how they can be reached. SmallPtrSet<CodeGenRegister*, 8> Orphans; // Clone inherited subregs and place duplicate entries in Orphans. // Here the order is important - earlier subregs take precedence. for (unsigned i = 0, e = SubList.size(); i != e; ++i) { CodeGenRegister *SR = RegBank.getReg(SubList[i]); const SubRegMap &Map = SR->getSubRegs(RegBank); // Add this as a super-register of SR now all sub-registers are in the list. // This creates a topological ordering, the exact order depends on the // order getSubRegs is called on all registers. SR->SuperRegs.push_back(this); for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE; ++SI) { if (!SubRegs.insert(*SI).second) Orphans.insert(SI->second); // Noop sub-register indexes are possible, so avoid duplicates. if (SI->second != SR) SI->second->SuperRegs.push_back(this); } } // Expand any composed subreg indices. // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process // expanded subreg indices recursively. for (unsigned i = 0; i != Indices.size(); ++i) { CodeGenSubRegIndex *Idx = Indices[i]; const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites(); CodeGenRegister *SR = SubRegs[Idx]; const SubRegMap &Map = SR->getSubRegs(RegBank); // Look at the possible compositions of Idx. // They may not all be supported by SR. for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(), E = Comps.end(); I != E; ++I) { SubRegMap::const_iterator SRI = Map.find(I->first); if (SRI == Map.end()) continue; // Idx + I->first doesn't exist in SR. // Add I->second as a name for the subreg SRI->second, assuming it is // orphaned, and the name isn't already used for something else. if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) continue; // We found a new name for the orphaned sub-register. SubRegs.insert(std::make_pair(I->second, SRI->second)); Indices.push_back(I->second); } } // Process the composites. ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices"); for (unsigned i = 0, e = Comps->size(); i != e; ++i) { DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i)); if (!Pat) throw TGError(TheDef->getLoc(), "Invalid dag '" + Comps->getElement(i)->getAsString() + "' in CompositeIndices"); DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator()); if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex")) throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " + Pat->getAsString()); CodeGenSubRegIndex *BaseIdx = RegBank.getSubRegIdx(BaseIdxInit->getDef()); // Resolve list of subreg indices into R2. CodeGenRegister *R2 = this; for (DagInit::const_arg_iterator di = Pat->arg_begin(), de = Pat->arg_end(); di != de; ++di) { DefInit *IdxInit = dynamic_cast<DefInit*>(*di); if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex")) throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " + Pat->getAsString()); CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(IdxInit->getDef()); const SubRegMap &R2Subs = R2->getSubRegs(RegBank); SubRegMap::const_iterator ni = R2Subs.find(Idx); if (ni == R2Subs.end()) throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() + " refers to bad index in " + R2->getName()); R2 = ni->second; } // Insert composite index. Allow overriding inherited indices etc. SubRegs[BaseIdx] = R2; // R2 is no longer an orphan. Orphans.erase(R2); } // Now Orphans contains the inherited subregisters without a direct index. // Create inferred indexes for all missing entries. // Work backwards in the Indices vector in order to compose subregs bottom-up. // Consider this subreg sequence: // // qsub_1 -> dsub_0 -> ssub_0 // // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register // can be reached in two different ways: // // qsub_1 -> ssub_0 // dsub_2 -> ssub_0 // // We pick the latter composition because another register may have [dsub_0, // dsub_1, dsub_2] subregs without neccessarily having a qsub_1 subreg. The // dsub_2 -> ssub_0 composition can be shared. while (!Indices.empty() && !Orphans.empty()) { CodeGenSubRegIndex *Idx = Indices.pop_back_val(); CodeGenRegister *SR = SubRegs[Idx]; const SubRegMap &Map = SR->getSubRegs(RegBank); for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE; ++SI) if (Orphans.erase(SI->second)) SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second; } // Initialize RegUnitList. A register with no subregisters creates its own // unit. Otherwise, it inherits all its subregister's units. Because // getSubRegs is called recursively, this processes the register hierarchy in // postorder. // // TODO: We currently assume all register units correspond to a named "leaf" // register. We should also unify register units for ad-hoc register // aliases. This can be done by iteratively merging units for aliasing // registers using a worklist. assert(RegUnits.empty() && "Should only initialize RegUnits once"); if (SubRegs.empty()) { RegUnits.push_back(RegBank.newRegUnit()); } else { for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); I != E; ++I) { // Strangely a register may have itself as a subreg (self-cycle) e.g. XMM. CodeGenRegister *SR = I->second; if (SR == this) { if (RegUnits.empty()) RegUnits.push_back(RegBank.newRegUnit()); continue; } // Merge the subregister's units into this register's RegUnits. mergeRegUnits(RegUnits, SR->RegUnits); } } return SubRegs; }