static void mb_cpu_realizefn(DeviceState *dev, Error **errp) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev); MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); cpu_reset(CPU(cpu)); mcc->parent_realize(dev, errp); }
static void mb_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); cpu_reset(cs); qemu_init_vcpu(cs); mcc->parent_realize(dev, errp); }
static void mb_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; uint8_t version_code = 0; int i = 0; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; } qemu_init_vcpu(cs); env->pvr.regs[0] = PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ | PVR0_USE_DCACHE_MASK; env->pvr.regs[2] = PVR2_D_OPB_MASK \ | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ | PVR2_I_LMB_MASK \ | PVR2_FPU_EXC_MASK \ | 0; for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) { if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) { version_code = mb_cpu_lookup[i].version_id; break; } } if (!version_code) { qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); } env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | (version_code << PVR0_VERSION_SHIFT) | (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); mcc->parent_realize(dev, errp); }