string Operator::declare(string name, const int width, bool isbus) throw(std::string) {
Signal* s;
ostringstream e;
// check the signals doesn't already exist
if(signalMap_.find(name) != signalMap_.end()) {
e << "ERROR in declare(), signal " << name<< " already exists";
throw e.str();
}
// construct the signal (lifeSpan and cycle are reset to 0 by the constructor)
s = new Signal(name, Signal::wire, width, isbus);
// define its cycle
if(isSequential())
s->setCycle(this->currentCycle_);
// add the signal to signalMap and signalList
signalList_.push_back(s);
signalMap_[name] = s ;
return name;
}
void Operator::outPortMap(Operator* op, string componentPortName, string actualSignalName) throw(std::string) {
Signal* formal;
Signal* s;
ostringstream e;
e << "ERROR in outPortMap(), "; // just in case
// check the signals doesn't already exist
if(signalMap_.find(actualSignalName) != signalMap_.end()) {
e << "signal " << actualSignalName << " already exists";
throw e.str();
}
try {
formal=op->getSignalByName(componentPortName);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if (formal->type()!=Signal::out){
e << "signal " << componentPortName << " of component " << op->getName()
<< " doesn't seem to be an output port";
throw e.str();
}
int width = formal -> width();
bool isbus = formal -> isBus();
// construct the signal (lifeSpan and cycle are reset to 0 by the constructor)
s = new Signal(actualSignalName, Signal::wire, width, isbus);
// define its cycle
if(isSequential())
s->setCycle( this->currentCycle_ + op->getPipelineDepth() );
// add the signal to signalMap and signalList
signalList_.push_back(s);
signalMap_[actualSignalName] = s ;
// add the mapping to the mapping list of Op
op->portMap_[componentPortName] = actualSignalName;
}