bool output_syntax(char *argv[], evl_module &module, evl_wires &wires, evl_components &components, evl_endmodule &endmodule)
{
std::string output_file_name = std::string(argv[1]) + ".syntax";
std::ofstream output_file(output_file_name.c_str());
if (!output_file)
{
std::cerr << "I can't write " << argv[1] << ".tokens ." << std::endl;
return false;
}
if (!module.type.empty())//if .evl has a module, output its name
{
output_file << "module " << module.type << std::endl;
}
if (!wires.empty())//if .evl has wires, output names
{
output_file << "wires " << wires.size() << std::endl;
for (evl_wires::iterator i = wires.begin(); i != wires.end(); ++i)
{
evl_wire wire = *i;
output_file << " wire " << wire.name << " " << wire.width << std::endl;
}
}
if (!components.empty())//if .evl has components, output pins, types and names
{
output_file << "components " << components.size() << std::endl;
for (evl_components::iterator i = components.begin(); i != components.end(); ++i)
{
evl_component component = *i;
output_file << " component " << component.type << " ";
if (component.name != "")// component name is optional
output_file << component.name << " ";
output_file << component.pins.size() << std::endl;
for (evl_pins::iterator j = component.pins.begin(); j != component.pins.end(); ++j)
{
evl_pin pin = *j;
output_file << " pin " << pin.name;
if (pin.bus_msb >= 0)
{
output_file << " " << pin.bus_msb;
}
if (pin.bus_lsb >= 0)
{
output_file << " " << pin.bus_lsb;
}
output_file << std::endl;
}
}
}
if (!endmodule.name.empty())//if .evl has endmodule, output it
{
output_file << "endmodule" << std::endl;
}
return true;
}
bool netlist::create_gates(const evl_components &comps,
const evl_wires_table &wires_table) {
for (evl_components::const_iterator iter = comps.begin(); iter != comps.end();
++iter) {
create_gate((*iter), wires_table);
}
return true;
}
bool netlist::create_gates(const evl_components &comps,
const evl_wires_table &wires_table)
{
for (evl_components::const_iterator ci = comps.begin(); ci !=comps.end(); ++ci)
{
evl_component c = (*ci);
create_gate(c, wires_table); // gate semantic vilation only output an error, does not stop the program
}
return true;
}
void display_components(ostream &out, const evl_components &components)
{
for (evl_components::const_iterator iter = components.begin(); iter != components.end(); ++iter)
{
out << "component " << iter->type << " " << iter->name << " " << iter->pins.size() << endl;
for (evl_pins::const_iterator it = iter->pins.begin(); it != iter->pins.end(); ++it)
{
out << "pin "<< it->name << " " << it->msb << " " << it->lsb << endl;
}
}
}
