void Cartridge::SaveState(State::Saver& state,const dword baseChunk) const
{
state.Begin( baseChunk );
board->SaveState( state, AsciiId<'M','P','R'>::V );
if (vs)
vs->SaveState( state, AsciiId<'V','S','S'>::V );
state.End();
}
void Ks202::SubSave(State::Saver& state) const
{
state.Begin( AsciiId<'K','0','2'>::V );
state.Begin( AsciiId<'R','E','G'>::V ).Write8( ctrl ).End();
const byte data[5] =
{
irq.unit.ctrl,
irq.unit.count & 0xFF,
irq.unit.count >> 8,
irq.unit.latch & 0xFF,
irq.unit.latch >> 8
};
state.Begin( AsciiId<'I','R','Q'>::V ).Write( data ).End();
state.End();
}
void Datach::Reader::SaveState(State::Saver& state,const dword baseChunk) const
{
if (Reader::IsTransferring())
{
NST_ASSERT( cycles != Cpu::CYCLE_MAX );
state.Begin( baseChunk );
state.Begin( AsciiId<'P','T','R'>::V ).Write8( stream - data ).End();
state.Begin( AsciiId<'D','A','T'>::V ).Compress( data ).End();
uint next;
if (cycles > cpu.GetCycles())
next = (cycles - cpu.GetCycles()) / cpu.GetClock();
else
next = 0;
state.Begin( AsciiId<'C','Y','C'>::V ).Write16( next ).End();
state.End();
}
}
void Tc0190fmcPal16r4::SubSave(State::Saver& state) const
{
state.Begin( AsciiId<'T','T','C'>::V );
irq.unit.SaveState( state, AsciiId<'I','R','Q'>::V );
state.End();
}
void Standard::SubSave(State::Saver& state) const
{
state.Begin( AsciiId<'J','Y','C'>::V );
{
const byte data[35] =
{
regs.ctrl[0],
regs.ctrl[1],
regs.ctrl[2],
regs.ctrl[3],
regs.mul[0],
regs.mul[1],
regs.tmp,
banks.prg[0],
banks.prg[1],
banks.prg[2],
banks.prg[3],
banks.chr[0] & 0xFF,
banks.chr[0] >> 8,
banks.chr[1] & 0xFF,
banks.chr[1] >> 8,
banks.chr[2] & 0xFF,
banks.chr[2] >> 8,
banks.chr[3] & 0xFF,
banks.chr[3] >> 8,
banks.chr[4] & 0xFF,
banks.chr[4] >> 8,
banks.chr[5] & 0xFF,
banks.chr[5] >> 8,
banks.chr[6] & 0xFF,
banks.chr[6] >> 8,
banks.chr[7] & 0xFF,
banks.chr[7] >> 8,
banks.nmt[0] & 0xFF,
banks.nmt[0] >> 8,
banks.nmt[1] & 0xFF,
banks.nmt[1] >> 8,
banks.nmt[2] & 0xFF,
banks.nmt[2] >> 8,
banks.nmt[3] & 0xFF,
banks.nmt[3] >> 8
};
state.Begin( AsciiId<'R','E','G'>::V ).Write( data ).End();
}
if (cartSwitches.IsPpuLatched())
state.Begin( AsciiId<'L','A','T'>::V ).Write8( banks.chrLatch[0] | banks.chrLatch[1] << 3 ).End();
{
const byte data[5] =
{
irq.enabled != 0,
irq.mode,
irq.prescaler & 0xFF,
irq.count,
irq.flip
};
state.Begin( AsciiId<'I','R','Q'>::V ).Write( data ).End();
}
state.End();
}