void MidiWinMM::removePort( MidiPort* port ) { for( SubMap::Iterator it = m_inputSubs.begin(); it != m_inputSubs.end(); ++it ) { it.value().removeAll( port ); } for( SubMap::Iterator it = m_outputSubs.begin(); it != m_outputSubs.end(); ++it ) { it.value().removeAll( port ); } MidiClient::removePort( port ); }
void MidiApple::removePort( MidiPort* port ) { qDebug("removePort displayName:'%s'",port->displayName().toLatin1().constData()); for( SubMap::Iterator it = m_inputSubs.begin(); it != m_inputSubs.end(); ++it ) { it.value().removeAll( port ); } for( SubMap::Iterator it = m_outputSubs.begin(); it != m_outputSubs.end(); ++it ) { it.value().removeAll( port ); } MidiClient::removePort( port ); }
void MidiWinMM::applyPortMode( MidiPort* port ) { // make sure no subscriptions exist which are not possible with // current port-mode if( !port->isInputEnabled() ) { for( SubMap::Iterator it = m_inputSubs.begin(); it != m_inputSubs.end(); ++it ) { it.value().removeAll( port ); } } if( !port->isOutputEnabled() ) { for( SubMap::Iterator it = m_outputSubs.begin(); it != m_outputSubs.end(); ++it ) { it.value().removeAll( port ); } } }
void MidiApple::applyPortMode( MidiPort* port ) { qDebug("applyPortMode displayName:'%s'",port->displayName().toLatin1().constData()); // make sure no subscriptions exist which are not possible with // current port-mode if( !port->isInputEnabled() ) { for( SubMap::Iterator it = m_inputSubs.begin(); it != m_inputSubs.end(); ++it ) { it.value().removeAll( port ); } } if( !port->isOutputEnabled() ) { for( SubMap::Iterator it = m_outputSubs.begin(); it != m_outputSubs.end(); ++it ) { it.value().removeAll( port ); } } }
// --------------------------------------------------------------- void LibraryDialog::slotSave() { stackedWidgets->setCurrentIndex(2); //message window libSaveName->setText(NameEdit->text() + ".lib"); ErrText->insert(tr("Saving library...")); if(!LibFile.open(QIODevice::WriteOnly)) { ErrText->append(tr("Error: Cannot create library!")); return; } QTextStream Stream; Stream.setDevice(&LibFile); Stream << "<Simgui Library " PACKAGE_VERSION " \"" << NameEdit->text() << "\">\n\n"; bool Success = true, ret; QString tmp; QTextStream ts(&tmp, QIODevice::WriteOnly); for (int i=0; i < SelectedNames.count(); i++) { ErrText->insert("\n=================\n"); QString description = ""; if(checkDescr->checkState() == Qt::Checked) description = Descriptions[i]; Stream << "<Component " + SelectedNames[i].section('.',0,0) + ">\n" << " <Description>\n" << description << "\n </Description>\n"; Schematic *Doc = new Schematic(0, SimguiSettings.SimguiWorkDir.filePath(SelectedNames[i])); ErrText->insert(tr("Loading subcircuit \"%1\".\n").arg(SelectedNames[i])); if(!Doc->loadDocument()) { // load document if possible delete Doc; ErrText->append(tr("Error: Cannot load subcircuit \"%1\"."). arg(SelectedNames[i])); break; } Doc->DocName = NameEdit->text() + "_" + SelectedNames[i]; Success = false; // save analog model tmp.truncate(0); Doc->isAnalog = true; ErrText->insert("\n"); ErrText->insert(tr("Creating Simgui netlist.\n")); ret = Doc->createLibNetlist(&ts, ErrText, -1); if(ret) { intoStream(Stream, tmp, "Model"); int error = 0; QStringList IFiles; SubMap::Iterator it = FileList.begin(); while(it != FileList.end()) { QString f = it.data().File; QString ifn, ofn; if(it.data().Type == "SCH") { ifn = f + ".lst"; ofn = ifn; } else if(it.data().Type == "CIR") { ifn = f + ".lst"; ofn = ifn; } if (!ifn.isEmpty()) error += intoFile(ifn, ofn, IFiles); it++; } FileList.clear(); if(!IFiles.isEmpty()) { Stream << " <ModelIncludes \"" << IFiles.join("\" \"") << "\">\n"; } Success = error > 0 ? false : true; } else { ErrText->insert("\n"); ErrText->insert(tr("Error: Cannot create netlist for \"%1\".\n").arg(SelectedNames[i])); } // save verilog model tmp.truncate(0); Doc->isVerilog = true; Doc->isAnalog = false; ErrText->insert("\n"); ErrText->insert(tr("Creating Verilog netlist.\n")); ret = Doc->createLibNetlist(&ts, ErrText, 0); if(ret) { intoStream(Stream, tmp, "VerilogModel"); int error = 0; QStringList IFiles; SubMap::Iterator it = FileList.begin(); while(it != FileList.end()) { QString f = it.data().File; QString ifn, ofn; if(it.data().Type == "SCH") { ifn = f + ".lst"; ofn = f + ".v"; } else if(it.data().Type == "VER") { ifn = f; ofn = ifn; } if (!ifn.isEmpty()) error += intoFile(ifn, ofn, IFiles); it++; } FileList.clear(); if(!IFiles.isEmpty()) { Stream << " <VerilogModelIncludes \"" << IFiles.join("\" \"") << "\">\n"; } Success = error > 0 ? false : true; } else { ErrText->insert("\n"); } // save vhdl model tmp.truncate(0); Doc->isVerilog = false; Doc->isAnalog = false; ErrText->insert(tr("Creating VHDL netlist.\n")); ret = Doc->createLibNetlist(&ts, ErrText, 0); if(ret) { intoStream(Stream, tmp, "VHDLModel"); int error = 0; QStringList IFiles; SubMap::Iterator it = FileList.begin(); while(it != FileList.end()) { QString f = it.data().File; QString ifn, ofn; if(it.data().Type == "SCH") { ifn = f + ".lst"; ofn = f + ".vhdl"; } else if(it.data().Type == "VHD") { ifn = f; ofn = ifn; } if (!ifn.isEmpty()) error += intoFile(ifn, ofn, IFiles); it++; } FileList.clear(); if(!IFiles.isEmpty()) { Stream << " <VHDLModelIncludes \"" << IFiles.join("\" \"") << "\">\n"; } Success = error > 0 ? false : true; } else { ErrText->insert("\n"); } Stream << " <Symbol>\n"; Doc->createSubcircuitSymbol(); Painting *pp; for(pp = Doc->SymbolPaints.first(); pp != 0; pp = Doc->SymbolPaints.next()) Stream << " <" << pp->save() << ">\n"; Stream << " </Symbol>\n" << "</Component>\n\n"; delete Doc; if(!Success) break; } // for LibFile.close(); if(!Success) { LibFile.remove(); ErrText->append(tr("Error creating library.")); return; } ErrText->append(tr("Successfully created library.")); }