static void
get_adc_config (uint32_t config[4])
{
config[2] = ADC_SQR1_NUM_CH(2);
switch (SYS_BOARD_ID)
{
case BOARD_ID_FST_01:
config[0] = 0;
config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
| ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5);
config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9);
break;
case BOARD_ID_OLIMEX_STM32_H103:
case BOARD_ID_STBEE:
config[0] = ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5)
| ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5);
config[1] = 0;
config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10)
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11);
break;
case BOARD_ID_STBEE_MINI:
config[0] = 0;
config[1] = ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5)
| ADC_SMPR2_SMP_AN2(ADC_SAMPLE_1P5);
config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1)
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2);
break;
case BOARD_ID_CQ_STARM:
case BOARD_ID_FST_01_00:
case BOARD_ID_MAPLE_MINI:
case BOARD_ID_STM32_PRIMER2:
case BOARD_ID_STM8S_DISCOVERY:
case BOARD_ID_ST_DONGLE:
case BOARD_ID_ST_NUCLEO_F103:
case BOARD_ID_NITROKEY_START:
default:
config[0] = 0;
config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
| ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5);
config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN1);
break;
}
}
/* HW dependent part.*/ ADC_TwoSamplingDelay_20Cycles, // cr1 ADC_CR2_SWSTART, // cr2 /** * here we configure all possible channels for slow mode. Some channels would not actually * be used hopefully that's fine to configure all possible channels. */ ADC_SMPR1_SMP_AN10(ADC_SAMPLING_SLOW) | ADC_SMPR1_SMP_AN11(ADC_SAMPLING_SLOW) | ADC_SMPR1_SMP_AN12(ADC_SAMPLING_SLOW) | ADC_SMPR1_SMP_AN13(ADC_SAMPLING_SLOW) | ADC_SMPR1_SMP_AN14(ADC_SAMPLING_SLOW) | ADC_SMPR1_SMP_AN15(ADC_SAMPLING_SLOW) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144) , // sample times for channels 10...18 ADC_SMPR2_SMP_AN0(ADC_SAMPLING_SLOW) | ADC_SMPR2_SMP_AN1(ADC_SAMPLING_SLOW) | ADC_SMPR2_SMP_AN2(ADC_SAMPLING_SLOW) | ADC_SMPR2_SMP_AN3(ADC_SAMPLING_SLOW) | ADC_SMPR2_SMP_AN4(ADC_SAMPLING_SLOW) | ADC_SMPR2_SMP_AN5(ADC_SAMPLING_SLOW) | ADC_SMPR2_SMP_AN6(ADC_SAMPLING_SLOW) | ADC_SMPR2_SMP_AN7(ADC_SAMPLING_SLOW) | ADC_SMPR2_SMP_AN8(ADC_SAMPLING_SLOW) | ADC_SMPR2_SMP_AN9(ADC_SAMPLING_SLOW) , // In this field must be specified the sample times for channels 0...9 0, // Conversion group sequence 13...16 + sequence length 0, // Conversion group sequence 7...12 0 // Conversion group sequence 1...6
/*
* ADC conversion group.
*/
static ADCConversionGroup adcgrpcfgSlow = { FALSE, 0, adc_callback_slow, NULL,
/* HW dependent part.*/
ADC_TwoSamplingDelay_20Cycles, // cr1
ADC_CR2_SWSTART, // cr2
ADC_SMPR1_SMP_AN10(MY_SAMPLING_SLOW) |
ADC_SMPR1_SMP_AN11(MY_SAMPLING_SLOW) |
ADC_SMPR1_SMP_AN12(MY_SAMPLING_SLOW) |
ADC_SMPR1_SMP_AN13(MY_SAMPLING_SLOW) |
ADC_SMPR1_SMP_AN14(MY_SAMPLING_SLOW) |
ADC_SMPR1_SMP_AN15(MY_SAMPLING_SLOW)
, // sample times for channels 10...18
ADC_SMPR2_SMP_AN0(MY_SAMPLING_SLOW) |
ADC_SMPR2_SMP_AN1(MY_SAMPLING_SLOW) |
ADC_SMPR2_SMP_AN3(MY_SAMPLING_SLOW) |
ADC_SMPR2_SMP_AN4(MY_SAMPLING_SLOW) |
ADC_SMPR2_SMP_AN5(MY_SAMPLING_SLOW) |
ADC_SMPR2_SMP_AN6(MY_SAMPLING_SLOW) |
ADC_SMPR2_SMP_AN7(MY_SAMPLING_SLOW) |
ADC_SMPR2_SMP_AN8(MY_SAMPLING_SLOW) |
ADC_SMPR2_SMP_AN9(MY_SAMPLING_SLOW)
, // In this field must be specified the sample times for channels 0...9
0, // Conversion group sequence 13...16 + sequence length
0, // Conversion group sequence 7...12
0 // Conversion group sequence 1...6
};
static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
/*
* ADC conversion group.
* Mode: Linear buffer
* Channels: IN0 (41.5 cycles sample time)
*/
static const ADCConversionGroup adcgrpcfg = {
FALSE, // Enables the circular buffer mode for the group.
ADC_GRP1_NUM_CHANNELS, // Number of the analog channels belonging to the conversion group.
NULL, // Callback function associated to the group
NULL, // Error callback
0, // ADC CR1 register initialization data
0, // ADC CR2 register initialization data
0, // ADC SMPR1 register initialization data
ADC_SMPR2_SMP_AN0(ADC_SAMPLE_41P5), // ADC SMPR2 register initialization data
ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),
0,
ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
};
void analog_init(void)
{
/*
* Initializes the ADC driver 1.
*/
adcStart(&ADCD1, NULL);
palSetGroupMode(GPIOA, PAL_PORT_BIT(0), 0, PAL_MODE_INPUT_ANALOG);
}
/*
* ADC conversion group.
* Mode: Linear buffer, 8 samples of 1 channel, SW triggered.
* Channels: IN11.
*/
static const ADCConversionGroup adcgrpcfg1 = {FALSE, //circular buffer mode
ADC_GRP1_NUM_CHANNELS, //Number of the analog channels
NULL, //Callback function (not needed here)
0, //Error callback
0, /* CR1 */
ADC_CR2_SWSTART, /* CR2 */
ADC_SMPR1_SMP_AN10(ADC_SAMPLE_84) | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_84)
| ADC_SMPR1_SMP_AN12(ADC_SAMPLE_84) | ADC_SMPR1_SMP_AN13(ADC_SAMPLE_84)
| ADC_SMPR1_SMP_AN14(ADC_SAMPLE_84) | ADC_SMPR1_SMP_AN15(ADC_SAMPLE_84), //sample times ch10-18
ADC_SMPR2_SMP_AN0(ADC_SAMPLE_84) | ADC_SMPR2_SMP_AN1(ADC_SAMPLE_84)
| ADC_SMPR2_SMP_AN2(ADC_SAMPLE_84) | ADC_SMPR2_SMP_AN3(ADC_SAMPLE_84)
| ADC_SMPR2_SMP_AN4(ADC_SAMPLE_84) | ADC_SMPR2_SMP_AN5(ADC_SAMPLE_84)
| ADC_SMPR2_SMP_AN6(ADC_SAMPLE_84) | ADC_SMPR2_SMP_AN7(ADC_SAMPLE_84)
| ADC_SMPR2_SMP_AN8(ADC_SAMPLE_84) | ADC_SMPR2_SMP_AN9(ADC_SAMPLE_84), //sample times ch0-9
ADC_SQR1_SQ13_N(ADC_CHANNEL_IN12) | ADC_SQR1_SQ14_N(ADC_CHANNEL_IN13)
| ADC_SQR1_SQ15_N(ADC_CHANNEL_IN14) | ADC_SQR1_SQ16_N(ADC_CHANNEL_IN15)
| ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), //SQR1: Conversion group sequence 13...16 + sequence length
ADC_SQR2_SQ7_N(ADC_CHANNEL_IN6) | ADC_SQR2_SQ8_N(ADC_CHANNEL_IN7)
| ADC_SQR2_SQ9_N(ADC_CHANNEL_IN8) | ADC_SQR2_SQ10_N(ADC_CHANNEL_IN9)
| ADC_SQR2_SQ11_N(ADC_CHANNEL_IN10) | ADC_SQR2_SQ12_N(ADC_CHANNEL_IN11), //SQR2: Conversion group sequence 7...12
ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN1)
| ADC_SQR3_SQ3_N(ADC_CHANNEL_IN2) | ADC_SQR3_SQ4_N(ADC_CHANNEL_IN3)
| ADC_SQR3_SQ5_N(ADC_CHANNEL_IN4) | ADC_SQR3_SQ6_N(ADC_CHANNEL_IN5) //SQR3: Conversion group sequence 1...6
};
*/
static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
/*
* ADC conversion group.
* Mode: Linear buffer, 8 samples of 1 channel, SW triggered.
* Channels: IN15 = PC5 = Morpho Nucleo CN10-pin 6.
*/
static const ADCConversionGroup adcgrpcfg1 = {
FALSE, // circular buffer mode
ADC_GRP1_NUM_CHANNELS, // Number of the analog channels
NULL, // Callback function (not needed here)
NULL, // Error callback
0, // CR1
ADC_CR2_SWSTART, // CR2
ADC_SMPR2_SMP_AN0(ADC_SAMPLE_3), // sample times ch10-18
0, // sample times ch0-9
ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),// SQR1: Conversion group sequence 13...16 + sequence length
0, // SQR2: Conversion group sequence 7...12
ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0) // SQR3: Conversion group sequence 1...6
};
int main(void) {
halInit();
chSysInit();
/*
* ADC init
*/
palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG);
0, // CR2
0 // DIER
};
/* Instrument conversion group */
static const ADCConversionGroup adc_con_group_1 = {
TRUE, /* circular mode */
1, /* number of channels in this con_group */
adc_inst_callback,
adc_error_callback,
0, /* ADC_CR1 */
/* cr2: Clock the ADC to timer 8 TRGO event*/
ADC_CR2_EXTSEL_SRC(14) | ADC_CR2_EXTEN_0,
/* smpr1+2: set all channels to 40 cycles per conversion (28+12) */
ADC_SMPR1_SMP_AN11(2)| ADC_SMPR1_SMP_AN12(2)| ADC_SMPR1_SMP_AN13(2),
ADC_SMPR2_SMP_AN0(2) | ADC_SMPR2_SMP_AN1(2) | ADC_SMPR2_SMP_AN2(2),
ADC_SQR1_NUM_CH(1), /* sqr1: set 1 channel in the group */
0, /* sqr2: no higher channels being sampled */
/* sqr3: set the two channels to sample */
ADC_SQR3_SQ1_N(INST_IN_CHN)
};
/* FX inputs conversion group */
static const ADCConversionGroup adc_con_group_2 = {
TRUE, /* circular mode */
3, /* number of channels in this con group */
adc_fx_callback,
adc_error_callback,
0, /* cr1 */
/* cr2: Clock the ADC to timer 3 TRGO event*/
ADC_CR2_EXTSEL_SRC(8) | ADC_CR2_EXTEN_0,
