//***************************************************************************** // //! @brief Enables the ITM //! //! This function enables the ARM ITM by setting the TRCENA bit in the DEMCR //! register. //! //! @return None. // //***************************************************************************** void am_hal_itm_enable(void) { if (g_ui32HALflags & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M) { return; } // // To be able to access ITM registers, set the Trace Enable bit // in the Debug Exception and Monitor Control Register (DEMCR). // AM_REG(SYSCTRL, DEMCR) |= AM_REG_SYSCTRL_DEMCR_TRCENA(1); while ( !(AM_REG(SYSCTRL, DEMCR) & AM_REG_SYSCTRL_DEMCR_TRCENA(1)) ); // // Write the key to the ITM Lock Access register to unlock the ITM_TCR. // AM_REGVAL(AM_REG_ITM_LOCKAREG_O) = AM_REG_ITM_LOCKAREG_KEYVAL; // // Set the enable bits in the ITM trace enable register, and the ITM // control registers to enable trace data output. // AM_REGVAL(AM_REG_ITM_TPR_O) = 0x0000000f; AM_REGVAL(AM_REG_ITM_TER_O) = 0xffffffff; // // Write to the ITM control and status register (don't enable yet). // AM_REGVAL(AM_REG_ITM_TCR_O) = AM_WRITE_SM(AM_REG_ITM_TCR_ATB_ID, 0x15) | AM_WRITE_SM(AM_REG_ITM_TCR_TS_FREQ, 1) | AM_WRITE_SM(AM_REG_ITM_TCR_TS_PRESCALE, 1) | AM_WRITE_SM(AM_REG_ITM_TCR_SWV_ENABLE, 1) | AM_WRITE_SM(AM_REG_ITM_TCR_DWT_ENABLE, 0) | AM_WRITE_SM(AM_REG_ITM_TCR_SYNC_ENABLE, 0) | AM_WRITE_SM(AM_REG_ITM_TCR_TS_ENABLE, 0) | AM_WRITE_SM(AM_REG_ITM_TCR_ITM_ENABLE, 1); }
//***************************************************************************** // //! @brief Configure the watchdog timer. //! //! @param psConfig - pointer to a configuration structure containing the //! desired watchdog settings. //! //! This function will set the watchdog configuration register based on the //! user's desired settings listed in the structure referenced by psConfig. If //! the structure indicates that watchdog interrupts are desired, this function //! will also set the interrupt enable bit in the configuration register. //! //! @note In order to actually receive watchdog interrupt and/or watchdog reset //! events, the caller will also need to make sure that the watchdog interrupt //! vector is enabled in the ARM NVIC, and that watchdog resets are enabled in //! the reset generator module. Otherwise, the watchdog-generated interrupt and //! reset events will have no effect. //! //! @return None. // //***************************************************************************** void am_hal_wdt_init(const am_hal_wdt_config_t *psConfig) { uint32_t ui32ConfigVal; uint16_t ui16IntCount, ui16ResetCount; bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET; bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT; // // Read the desired settings from the psConfig structure. // ui16IntCount = psConfig->ui16InterruptCount; ui16ResetCount = psConfig->ui16ResetCount; // // Write the interrupt and reset count values to a temporary variable. // // Accept the passed Config value, but clear the Counts that we are about to set. ui32ConfigVal = psConfig->ui32Config & ~(AM_REG_WDT_CFG_INTVAL_M | AM_REG_WDT_CFG_RESVAL_M); ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_INTVAL, ui16IntCount); ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_RESVAL, ui16ResetCount); // // If interrupts should be enabled, set the appropriate bit in the // temporary variable. Also, enable the interrupt in INTEN register in the // watchdog module. // if ( bInterruptEnabled ) { // // Enable the watchdog interrupt if the configuration calls for them. // AM_REGn(WDT, 0, INTEN) |= AM_REG_WDT_INTEN_WDT_M; } else { // // Disable the watchdog interrupt if the configuration doesn't call for // watchdog interrupts. // AM_REGn(WDT, 0, INTEN) &= ~AM_REG_WDT_INTEN_WDT_M; } // // If resets should be enabled, set the appropriate bit in the temporary // variable. // if ( bResetEnabled ) { // // Also enable watchdog resets in the reset module. // AM_REG(RSTGEN, CFG) |= AM_REG_RSTGEN_CFG_WDREN_M; } else { // // Disable watchdog resets in the reset module. // AM_REG(RSTGEN, CFG) &= ~AM_REG_RSTGEN_CFG_WDREN_M; } // // Check for a user specified clock select. If none specified then // set 128Hz. // if ( !(psConfig->ui32Config & AM_REG_WDT_CFG_CLKSEL_M) ) { ui32ConfigVal |= AM_REG_WDT_CFG_CLKSEL_128HZ; } // // Write the saved value to the watchdog configuration register. // AM_REGn(WDT, 0, CFG) = ui32ConfigVal; }