static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 column bits */
| AT91C_DDRC2_NR_14 /* 14 row bits(8K)*/
| AT91C_DDRC2_CAS_3 /* CAS Latency 3 */
| AT91C_DDRC2_EBISHARE /* DQM is shared with other controller */
| AT91C_DDRC2_DLL_RESET_DISABLED); /* DLL not reset*/
ddramc_config->rtr = 0x24B;
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
| AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
| AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TRRD_(1) /* 1 * 7.5 = 7.5 ns */
| AT91C_DDRC2_TWTR_(1) /* 1 clock cycle */
| AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
| AT91C_DDRC2_TXSNR_(16) /* 16 * 7.5 = 120 ns */
| AT91C_DDRC2_TRFC_(14)); /* 14 * 7.5 = 142 ns */
ddramc_config->t2pr = (AT91C_DDRC2_TRTP_(1) /* 1 * 7.5 = 7.5 ns */
| AT91C_DDRC2_TRPA_(0) /* 0 * 7.5 = 0 ns */
| AT91C_DDRC2_TXARDS_(7) /* 7 clock cycles */
| AT91C_DDRC2_TXARD_(2)); /* 2 clock cycles */
}
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS |
AT91C_DDRC2_MD_DDR3_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 |
AT91C_DDRC2_NR_14 |
AT91C_DDRC2_CAS_5 |
AT91C_DDRC2_DIS_DLL_DISABLED |
AT91C_DDRC2_WEAK_STRENGTH_RZQ7 |
AT91C_DDRC2_NB_BANKS_8 |
AT91C_DDRC2_DECOD_INTERLEAVED |
AT91C_DDRC2_UNAL_SUPPORTED);
/*
* According to MT41K128M16 datasheet
* Maximum fresh period: 64ms, refresh count: 8k
*/
#ifdef CONFIG_BUS_SPEED_166MHZ
/* Refresh Timer is (64ms / 8k) * 166MHz = 1297(0x511) */
ddramc_config->rtr = 0x511;
/*
* According to the sama5d2 datasheet and the following values:
* T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s
* Warning: note that the values T driftrate and V driftrate are dependent on
* the application environment.
* ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s
* If tref is 7.8us, we have: 400000 / 7.8 = 51282(0xC852)
* */
ddramc_config->cal_mr4r = AT91C_DDRC2_COUNT_CAL(0xC852);
/* DDR3 ZQCS */
ddramc_config->tim_calr = AT91C_DDRC2_ZQCS(64);
/* Assume timings for 8ns min clock period */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) |
AT91C_DDRC2_TRCD_(3) |
AT91C_DDRC2_TWR_(4) |
AT91C_DDRC2_TRC_(9) |
AT91C_DDRC2_TRP_(3) |
AT91C_DDRC2_TRRD_(4) |
AT91C_DDRC2_TWTR_(4) |
AT91C_DDRC2_TMRD_(4));
ddramc_config->t1pr = (AT91C_DDRC2_TRFC_(27) |
AT91C_DDRC2_TXSNR_(29) |
AT91C_DDRC2_TXSRD_(0) |
AT91C_DDRC2_TXP_(3));
ddramc_config->t2pr = (AT91C_DDRC2_TXARD_(0) |
AT91C_DDRC2_TXARDS_(0) |
AT91C_DDRC2_TRPA_(0) |
AT91C_DDRC2_TRTP_(4) |
AT91C_DDRC2_TFAW_(7));
#else
#error "No CLK setting defined"
#endif
}
/* Using the Micron MT47H64M16HR-3 */
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 column bits(1K) */
| AT91C_DDRC2_NR_13 /* 13 row bits (8K) */
| AT91C_DDRC2_CAS_3 /* CAS Latency 3 */
| AT91C_DDRC2_NB_BANKS_8 /* 8 banks */
| AT91C_DDRC2_DLL_RESET_DISABLED /* DLL not reset */
| AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/
/*
* Make sure to uncomment the following line if the DDR controller
* shares the EBI with another memory controller (SMC, NAND,..).
* For instance, AT91C_DDRC2_EBISHARE shall be set if NAND flash
* data line 0 is positioned on EBI data line 0 (AT91C_EBI_NFD0_ON_D16 bit
* cleared in CCFG_EBICSA register).
*
* For Atmel AT91SAM9x5-EK revision B onwards, this AT91C_DDRC2_EBISHARE bit
* is cleared because the NAND flash data line 0 is positioned on EBI
* data line number 16 (AT91C_EBI_NFD0_ON_D16 bit set in CCFG_EBICSA
* register). Only the DDR controller function is thus used on lower
* EBI data lines.
*/
//ddramc_config->cr |= AT91C_DDRC2_EBISHARE; /* DQM is shared with other controller */
/*
* The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
* With a 133 MHz frequency, the refresh timer count register must to be
* set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
* or (7.81 x 133 MHz) ~ 1040 i.e. 0x410.
*/
ddramc_config->rtr = 0x411; /* Refresh timer: 7.8125us */
/* One clock cycle @ 133 MHz = 7.5 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
| AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
| AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
| AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
| AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns*/
| AT91C_DDRC2_TRFC_(18)); /* 18 * 7.5 = 135 ns */
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7) /* 7 * 7.5 = 52.5 ns */
| AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TRPA_(3) /* 3 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TXARDS_(7) /* 7 clock cycles */
| AT91C_DDRC2_TXARD_(2)); /* 2 clock cycles */
}
static void lpddr2_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS |
AT91C_DDRC2_MD_LPDDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 |
AT91C_DDRC2_NR_14 |
AT91C_DDRC2_CAS_3 |
AT91C_DDRC2_ZQ_SHORT |
AT91C_DDRC2_NB_BANKS_8 |
AT91C_DDRC2_UNAL_SUPPORTED);
ddramc_config->lpddr2_lpr = AT91C_LPDDRC2_DS(0x03);
#ifdef CONFIG_BUS_SPEED_166MHZ
/*
* The MT42128M32 refresh window: 32ms
* Required number of REFRESH commands(MIN): 8192
* (32ms / 8192) * 166MHz = 0x288.
*/
ddramc_config->rtr = 0x288;
/* 90n short calibration: ZQCS */
ddramc_config->tim_calr = AT91C_DDRC2_ZQCS(12);
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(7) |
AT91C_DDRC2_TRCD_(3) |
AT91C_DDRC2_TWR_(3) |
AT91C_DDRC2_TRC_(11) |
AT91C_DDRC2_TRP_(4) |
AT91C_DDRC2_TRRD_(2) |
AT91C_DDRC2_TWTR_(2) |
AT91C_DDRC2_TMRD_(3));
ddramc_config->t1pr = (AT91C_DDRC2_TRFC_(35) |
AT91C_DDRC2_TXSNR_(37) |
AT91C_DDRC2_TXSRD_(0) |
AT91C_DDRC2_TXP_(2));
ddramc_config->t2pr = (AT91C_DDRC2_TXARD_(0) |
AT91C_DDRC2_TXARDS_(0) |
AT91C_DDRC2_TRPA_(0) |
AT91C_DDRC2_TRTP_(2) |
AT91C_DDRC2_TFAW_(9));
#else
#error "No CLK setting defined"
#endif
}
static void lpddr1_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS |
AT91C_DDRC2_MD_LP_DDR_SDRAM);
/* 14 Row bits, 10 Column bits */
ddramc_config->cr = (AT91C_DDRC2_NC_DDR11_SDR10 |
AT91C_DDRC2_NR_14 |
AT91C_DDRC2_CAS_3 |
AT91C_DDRC2_NDQS_DISABLED |
AT91C_DDRC2_UNAL_SUPPORTED);
ddramc_config->lpr = 0;
/*
* According to MT46H128M16LF-5 IT datasheet
* Maximum fresh period: 64ms, refresh count: 8k
*/
#ifdef CONFIG_BUS_SPEED_166MHZ
/* Refresh Timer is (64ms / 8k) * 166MHz = 1297(0x511) */
ddramc_config->rtr = 0x511;
/* Assume the timings for 6ns min clock period */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(7) |
AT91C_DDRC2_TRCD_(3) |
AT91C_DDRC2_TWR_(3) |
AT91C_DDRC2_TRC_(10) |
AT91C_DDRC2_TRP_(3) |
AT91C_DDRC2_TRRD_(2) |
AT91C_DDRC2_TWTR_(2) |
AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TRFC_(12) |
AT91C_DDRC2_TXSNR_(19) |
AT91C_DDRC2_TXSRD_(0) |
AT91C_DDRC2_TXP_(2));
ddramc_config->t2pr = (AT91C_DDRC2_TXARD_(0) |
AT91C_DDRC2_TXARDS_(0) |
AT91C_DDRC2_TRPA_(0) |
AT91C_DDRC2_TRTP_(0) |
AT91C_DDRC2_TFAW_(0));
#else
#error "No CLK setting defined"
#endif
}
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
| AT91C_DDRC2_MD_DDR3_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
| AT91C_DDRC2_NR_14
| AT91C_DDRC2_CAS_5
| AT91C_DDRC2_DIS_DLL_DISABLED
| AT91C_DDRC2_WEAK_STRENGTH_RZQ7
| AT91C_DDRC2_NB_BANKS_8
| AT91C_DDRC2_DECOD_INTERLEAVED
| AT91C_DDRC2_UNAL_SUPPORTED);
/*
* According to MT41K128M16 datasheet
* Maximum fresh period: 64ms, refresh count: 8k
*/
#ifdef CONFIG_BUS_SPEED_166MHZ
/* Refresh Timer is (64ms / 8k) * 166MHz = 1297(0x511) */
ddramc_config->rtr = 0x511;
/* Assume timings for 8ns min clock period */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(4)
| AT91C_DDRC2_TRC_(9)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(4)
| AT91C_DDRC2_TWTR_(4)
| AT91C_DDRC2_TMRD_(4));
ddramc_config->t1pr = (AT91C_DDRC2_TRFC_(27)
| AT91C_DDRC2_TXSNR_(29)
| AT91C_DDRC2_TXSRD_(0)
| AT91C_DDRC2_TXP_(3));
ddramc_config->t2pr = (AT91C_DDRC2_TXARD_(0)
| AT91C_DDRC2_TXARDS_(0)
| AT91C_DDRC2_TRPA_(0)
| AT91C_DDRC2_TRTP_(4)
| AT91C_DDRC2_TFAW_(7));
#else
#error "No CLK setting defined"
#endif
}
static void lpddr2_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
| AT91C_DDRC2_MD_LPDDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
| AT91C_DDRC2_NR_14
| AT91C_DDRC2_CAS_3
| AT91C_DDRC2_ZQ_SHORT
| AT91C_DDRC2_NB_BANKS_8
| AT91C_DDRC2_UNAL_SUPPORTED);
ddramc_config->lpddr2_lpr = AT91C_LPDDRC2_DS(0x03);
/* 90n short calibration: ZQCS */
ddramc_config->tim_calr = AT91C_DDRC2_ZQCS(12);
/*
* The MT42128M32 refresh window: 32ms
* Required number of REFRESH commands(MIN): 8192
* (32ms / 8192) * 132MHz = 514 i.e. 0x202
*/
ddramc_config->rtr = 0x202;
ddramc_config->cal_mr4r = AT91C_DDRC2_COUNT_CAL(0xC852);
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6)
| AT91C_DDRC2_TRCD_(2)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(8)
| AT91C_DDRC2_TRP_(2)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(3));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSNR_(18)
| AT91C_DDRC2_TRFC_(17));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(8)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(1)
| AT91C_DDRC2_TXARD_(1));
}
static void lpddr3_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS |
AT91C_DDRC2_MD_LPDDR3_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 |
AT91C_DDRC2_NR_14 |
AT91C_DDRC2_CAS_3 |
AT91C_DDRC2_ZQ_INIT |
AT91C_DDRC2_NB_BANKS_8 |
AT91C_DDRC2_DECOD_SEQUENTIAL |
AT91C_DDRC2_UNAL_SUPPORTED);
ddramc_config->lpddr2_lpr = AT91C_LPDDRC2_DS(0x04);
#ifdef CONFIG_BUS_SPEED_166MHZ
/* The low-power DDR3-SDRAM device requires a refresh every 3.9 us.*/
ddramc_config->rtr = 0x288;
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(7) |
AT91C_DDRC2_TRCD_(3) |
AT91C_DDRC2_TWR_(3) |
AT91C_DDRC2_TRC_(11) |
AT91C_DDRC2_TRP_(4) |
AT91C_DDRC2_TRRD_(2) |
AT91C_DDRC2_TWTR_(4) |
AT91C_DDRC2_TMRD_(10));
ddramc_config->t1pr = (AT91C_DDRC2_TRFC_(35) |
AT91C_DDRC2_TXSNR_(37) |
AT91C_DDRC2_TXSRD_(0) |
AT91C_DDRC2_TXP_(2));
ddramc_config->t2pr = (AT91C_DDRC2_TXARD_(0) |
AT91C_DDRC2_TXARDS_(0) |
AT91C_DDRC2_TRPA_(0) |
AT91C_DDRC2_TRTP_(4) |
AT91C_DDRC2_TFAW_(9));
#else
#error "No CLK setting defined"
#endif
}
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
| AT91C_DDRC2_NR_14
| AT91C_DDRC2_CAS_3
| AT91C_DDRC2_DLL_RESET_DISABLED
| AT91C_DDRC2_DIS_DLL_DISABLED
| AT91C_DDRC2_NB_BANKS_8
| AT91C_DDRC2_DECOD_INTERLEAVED
| AT91C_DDRC2_UNAL_SUPPORTED);
#if defined(CONFIG_BUS_SPEED_133MHZ)
ddramc_config->rtr = 0x208;
/* One clock cycle @ 133 MHz = 7.5 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6)
| AT91C_DDRC2_TRCD_(2)
| AT91C_DDRC2_TWR_(2)
| AT91C_DDRC2_TRC_(8)
| AT91C_DDRC2_TRP_(2)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(19)
| AT91C_DDRC2_TRFC_(17));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(5)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(2)
| AT91C_DDRC2_TXARDS_(2)
| AT91C_DDRC2_TXARD_(8));
#elif defined(CONFIG_BUS_SPEED_148MHZ)
ddramc_config->rtr = 0x243;
/* One clock cycle @ 148 MHz = 6.7 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(7)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(9)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(31)
| AT91C_DDRC2_TRFC_(30));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(8)
| AT91C_DDRC2_TXARD_(8));
#elif defined(CONFIG_BUS_SPEED_170MHZ)
ddramc_config->rtr = 0x229;
/* One clock cycle @ 170 MHz = 5.9 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(7)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(10)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(24)
| AT91C_DDRC2_TRFC_(22));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(6)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(2)
| AT91C_DDRC2_TXARD_(8));
#elif defined(CONFIG_BUS_SPEED_176MHZ)
ddramc_config->rtr = 0x2b0;
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(8)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(10)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(25)
| AT91C_DDRC2_TRFC_(23));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(2)
| AT91C_DDRC2_TXARD_(8));
#else
#error "No CLK setting defined"
#endif
}
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
| AT91C_DDRC2_NR_13
| AT91C_DDRC2_CAS_3
| AT91C_DDRC2_DLL_RESET_DISABLED
| AT91C_DDRC2_DIS_DLL_DISABLED
| AT91C_DDRC2_ENRDM_ENABLE
| AT91C_DDRC2_NB_BANKS_8
| AT91C_DDRC2_NDQS_DISABLED
| AT91C_DDRC2_DECOD_INTERLEAVED
| AT91C_DDRC2_UNAL_SUPPORTED);
#if defined(CONFIG_BUS_SPEED_133MHZ)
/*
* The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
* With a 133 MHz frequency, the refresh timer count register must to be
* set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
* or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
*/
ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
/* One clock cycle @ 133 MHz = 7.5 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
| AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
| AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
| AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
| AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns */
| AT91C_DDRC2_TRFC_(17)); /* 17 * 7.5 = 127.5 ns */
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(6) /* 6 * 7.5 = 45 ns */
| AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TRPA_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TXARDS_(8) /* = TXARD */
| AT91C_DDRC2_TXARD_(8)); /* MR12 = 1 */
#elif defined(CONFIG_BUS_SPEED_166MHZ)
/*
* The DDR2-SDRAM device requires a refresh of all rows every 64ms.
* ((64ms) / 8192) * 166MHz = 1296 i.e. 0x510
*/
ddramc_config->rtr = 0x510;
/* One clock cycle @ 166 MHz = 6.0 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(8) /* 8 * 6 = 48 ns */
| AT91C_DDRC2_TRCD_(3) /* 3 * 6 = 18 ns */
| AT91C_DDRC2_TWR_(3) /* 3 * 6 = 18 ns */
| AT91C_DDRC2_TRC_(10) /* 10 * 6 = 60 ns */
| AT91C_DDRC2_TRP_(3) /* 3 * 6 = 18 ns */
| AT91C_DDRC2_TRRD_(2) /* 2 * 6 = 12 ns */
| AT91C_DDRC2_TWTR_(2) /* 2 clock cycles */
| AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 * 6 = 12ns */
| AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
| AT91C_DDRC2_TXSNR_(23) /* 23 * 6 = 138 ns */
| AT91C_DDRC2_TRFC_(22)); /* 22 * 6 = 132 ns */
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(8) /* 45 ns */
| AT91C_DDRC2_TRTP_(2) /* 2 * 6 = 15ns */
| AT91C_DDRC2_TRPA_(3) /* 15 ns */
| AT91C_DDRC2_TXARDS_(8) /* = TXARD */
| AT91C_DDRC2_TXARD_(8)); /* 8 clock cycles */
#else
#error "No bus clock provided!"
#endif
}
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 colum bit */
| AT91C_DDRC2_NR_13
| AT91C_DDRC2_CAS_3
| AT91C_DDRC2_DLL_RESET_DISABLED
| AT91C_DDRC2_DIS_DLL_DISABLED
| AT91C_DDRC2_NB_BANKS_4
| AT91C_DDRC2_DECOD_INTERLEAVED
| AT91C_DDRC2_UNAL_SUPPORTED);
#if defined(CONFIG_BUS_SPEED_176MHZ)
ddramc_config->rtr = 0x55f;
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(8)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(10)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(21)
| AT91C_DDRC2_TRFC_(19));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(8)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(8)
| AT91C_DDRC2_TXARD_(8));
#elif defined(CONFIG_BUS_SPEED_200MHZ)
ddramc_config->rtr = 0x61b;
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(9)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(11)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(23)
| AT91C_DDRC2_TRFC_(21));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(10)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(4)
| AT91C_DDRC2_TXARDS_(8)
| AT91C_DDRC2_TXARD_(2));
#else
#error "No CLK setting defined"
#endif
}