static void __ramfunc tc_fdt_irq(void)
{
portSAVE_CONTEXT();
//vLedSetGreen(1);
u_int32_t sr = tcfdt->TC_SR;
DEBUGP("tc_fdt_irq: TC2_SR=0x%08x TC2_CV=0x%08x ",
sr, tcfdt->TC_CV);
if (sr & AT91C_TC_ETRGS) {
DEBUGP("Ext_trigger ");
}
if (sr & AT91C_TC_CPAS) {
DEBUGP("FDT_expired ");
}
if (sr & AT91C_TC_CPCS) {
DEBUGP("Compare_C ");
}
DEBUGPCR("");
AT91F_AIC_ClearIt(AT91C_ID_TC2);
AT91F_AIC_AcknowledgeIt();
//vLedSetGreen(0);
portRESTORE_CONTEXT();
}
//*=========================================================
//* INIT
//*=========================================================
//*----------------------------------------------------------------------------
//* \fn AT91F_SetTwiClock
//* \brief Initialization
//*----------------------------------------------------------------------------
//===============================================================================================
__arm void AT91_TWI_ISR(void)
{
unsigned int status;
volatile int SizeNotWrited;
portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE;
// What caused the interrupt?
status = AT91C_BASE_TWI->TWI_SR &= AT91C_BASE_TWI->TWI_IMR;
SizeNotWrited = SizeNotWrited;
if(status & AT91C_TWI_OVRE)
{
AT91F_TWI_DisableIt(AT91C_BASE_TWI,AT91C_TWI_TXRDY | AT91C_TWI_NACK | AT91C_TWI_TXCOMP|AT91C_TWI_RXRDY );
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP;
// SYSTEM_ERROR(TWI_OVRE_Error);
xTaskWokenByPost = xQueueSendFromISR( TWI_QUEUE, &TWI_Bytes2Transfere, xTaskWokenByPost );
TWI_TransferStatus = FREE;
}else
if (status & AT91C_TWI_NACK)
{
AT91F_TWI_DisableIt(AT91C_BASE_TWI,AT91C_TWI_TXRDY | AT91C_TWI_NACK | AT91C_TWI_TXCOMP|AT91C_TWI_RXRDY );
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP;
// SYSTEM_ERROR(TWI_NACK_Error);
xTaskWokenByPost = xQueueSendFromISR( TWI_QUEUE, &TWI_Bytes2Transfere, xTaskWokenByPost );
TWI_TransferStatus = FREE;
}else
{
switch(TWI_TransferStatus)
{
case ON_READ_DATA:
if(status & AT91C_TWI_TXCOMP)
{ // next char can be read
if(TWI_Bytes2Transfere-- > 1)
{
*(TWI_DataPointer++) = AT91C_BASE_TWI->TWI_RHR;
if(TWI_ConitiosTransaction)
{
TWI_ConitiosTransaction = 0;
TWI->TWI_MMR = TWI_DeviceAddr | AT91C_TWI_IADRSZ_NO | AT91C_TWI_MREAD;
// AT91F_TWI_EnableIt(TWI, AT91C_TWI_TXCOMP | AT91C_TWI_NACK );
// AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START | AT91C_TWI_MSEN | AT91C_TWI_STOP ;
}
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START | AT91C_TWI_MSEN | AT91C_TWI_STOP;
} else
{
*(TWI_DataPointer++) = AT91C_BASE_TWI->TWI_RHR;
AT91F_TWI_DisableIt(AT91C_BASE_TWI,AT91C_TWI_TXCOMP|AT91C_TWI_NACK);
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP;
xTaskWokenByPost = xQueueSendFromISR( TWI_QUEUE, &TWI_Bytes2Transfere, xTaskWokenByPost );
TWI_TransferStatus = FREE;
//TWI_TransferStatus = FREE;
}
}else
{
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP;
}
//-----------------------------
break;
case ON_WRITE_DATA:
if(status& AT91C_TWI_TXRDY)
{ // next char can be write
if(TWI_Bytes2Transfere-- > 1)
{
AT91C_BASE_TWI->TWI_THR = *(TWI_DataPointer++) ;
} else
{
AT91F_TWI_DisableIt(AT91C_BASE_TWI,AT91C_TWI_TXRDY|AT91C_TWI_NACK);
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP;
xTaskWokenByPost = xQueueSendFromISR( TWI_QUEUE, &TWI_Bytes2Transfere, xTaskWokenByPost );
TWI_TransferStatus = FREE;
}
}
// TWI_TransferStatus = FREE;
//-----------------------------
break;
default:
AT91F_TWI_DisableIt(AT91C_BASE_TWI,AT91C_TWI_RXRDY|AT91C_TWI_TXCOMP|AT91C_TWI_NACK);
xTaskWokenByPost = xQueueSendFromISR( TWI_QUEUE, &TWI_Bytes2Transfere, xTaskWokenByPost );
TWI_TransferStatus = FREE;
}
}
portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) );
AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
// AT91C_BASE_AIC->AIC_EOICR = 0;
}
