예제 #1
0
static void pm9g45_nand_hw_init(void)
{
    unsigned long csa;
    struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
    struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
    struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

    /* Enable CS3 */
    csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
    writel(csa, &matrix->ccr[6]);

    /* Configure SMC CS3 for NAND/SmartMedia */
    writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
           AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
           &smc->cs[3].setup);

    writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
           AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
           &smc->cs[3].pulse);

    writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
           &smc->cs[3].cycle);

    writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
           AT91_SMC_MODE_EXNW_DISABLE |
           AT91_SMC_MODE_DBW_8 |
           AT91_SMC_MODE_TDF_CYCLE(3),
           &smc->cs[3].mode);

    writel(1 << ATMEL_ID_PIOC, &pmc->pcer);

#ifdef CONFIG_SYS_NAND_READY_PIN
    /* Configure RDY/BSY */
    gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
#endif

    /* Enable NandFlash */
    gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
예제 #2
0
static void sbc35_a9g20_nand_hw_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	unsigned long csa;

	/* Enable CS3 */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		AT91_SMC_MODE_DBW_8 |
#endif
		AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
예제 #3
0
파일: gurnard.c 프로젝트: bradfa/u-boot
/**
 * Initialise the memory bus settings so that we can talk to the
 * memory mapped FPGA
 */
static int fpga_hw_init(void)
{
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	int i;

	setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);

	at91_set_a_periph(2, 4, 0); /* EBIA21 */
	at91_set_a_periph(2, 5, 0); /* EBIA22 */
	at91_set_a_periph(2, 6, 0); /* EBIA23 */
	at91_set_a_periph(2, 7, 0); /* EBIA24 */
	at91_set_a_periph(2, 12, 0); /* EBIA25 */
	for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
		at91_set_a_periph(2, i, 0);

	/* configure SMC cs0 for FPGA access timing */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
	       AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
	       &smc->cs[0].setup);
	writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
	       AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
	       &smc->cs[0].pulse);
	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
	       &smc->cs[0].cycle);
	writel(AT91_SMC_MODE_BAT |
	       AT91_SMC_MODE_EXNW_DISABLE |
	       AT91_SMC_MODE_DBW_32 |
	       AT91_SMC_MODE_TDF |
	       AT91_SMC_MODE_TDF_CYCLE(2),
	       &smc->cs[0].mode);

	/* Do a write to within EBI_CS1 to enable the SDCK */
	writel(0, ATMEL_BASE_CS1);

	return 0;
}
예제 #4
0
/*
 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
 * controller debugging
 * The ET1100 is located at physical address 0x70000000
 * Its process memory is located at physical address 0x70001000
 */
static void otc570_ethercat_hw_init(void)
{
	at91_smc_t	*smc1 	= (at91_smc_t *) ATMEL_BASE_SMC1;

	/* Configure SMC EBI1_CS0 for EtherCAT */
	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
		&smc1->cs[0].setup);
	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
		AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
		&smc1->cs[0].pulse);
	writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
		&smc1->cs[0].cycle);
	/*
	 * Configure behavior at external wait signal, byte-select mode, 16 bit
	 * data bus width, none data float wait states and TDF optimization
	 */
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
		AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
		AT91_SMC_MODE_TDF, &smc1->cs[0].mode);

	/* Configure RDY/BSY */
	at91_set_b_periph(AT91_PIO_PORTE, 20, 0);	/* EBI1_NWAIT */
}