//////////////////////////////////////////////////// // 功能: 关闭声音设备 // 输入: // 输出: // 返回: // 说明: //////////////////////////////////////////////////// void CloseMediaDevice(char channel) { int arg; int time; arg = ((channel == 0) ? RECORD_CHANNEL : PLAYBACK_CHANNEL ); //等待DMA结束 time = 0; while( INREG32(A_DMA_DTC(arg)) ) { #ifdef KPRINTF_DEF kprintf("close media device : count = %x\n",INREG32(A_DMA_DTC(arg))); #endif sTimerSleep(10, NULL); //加入延迟处理,防止死锁 time++; if( time > 10 ) { kdebug(mod_media, PRINT_WARNING, "close media device timer out\n"); break; } } //stop dma CLRREG32(A_DMA_DCS(arg), DCS_AR | DCS_HLT | DCS_CTE | DCS_CT); //close aic CLRREG32(AIC_CR, AIC_CR_ERPL); SETREG32(AIC_CR, AIC_CR_FLUSH_FIFO); OUTREG32(AIC_SR, 0x00000000); #ifndef CODEC_ALWAYS_OPEN CloseMediaCodecDevice(); #endif }
void dma_nowait_cpyinit() { CLRREG32(A_CPM_CLKGR, ( 1 << 12 )); SETREG32(A_DMA_DMAC(DMA_CPY_CHANNEL / 6),DMAC_DMA_EN); OUTREG32(A_DMA_DCKE(DMA_CPY_CHANNEL / 6),(1 << (DMA_CPY_CHANNEL % 6)));//Open channel clock CLRREG32(A_DMA_DMAC(DMA_CPY_CHANNEL / 6), (DMAC_HALT | DMAC_ADDR_ERR));//Ensure DMAC.AR = 0,DMAC.HLT = 0 CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_AR | DCS_HLT | DCS_TT | DCS_INV); // Ensure DCSn.AR = 0, DCSn.HLT = 0, DCSn.TT = 0, DCSn.INV = 0 OUTREG32(A_DMA_DTC(DMA_CPY_CHANNEL), 0);//DTCn = 0 CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE); SETREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_NDES); }
void dma_copy_nowait(void *tar,void *src,int size) { int timeout = 0x1000000; while ((!(INREG32(A_DMA_DCS(DMA_CPY_CHANNEL)) & DCS_TT)) && (timeout--)); CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE); OUTREG32(A_DMA_DSA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)src)); OUTREG32(A_DMA_DTA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)tar)); OUTREG32(A_DMA_DTC(DMA_CPY_CHANNEL), size / 32); OUTREG32(A_DMA_DRT(DMA_CPY_CHANNEL), DRT_AUTO); OUTREG32(A_DMA_DCM(DMA_CPY_CHANNEL), (DCM_SAI| DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT | DCM_TSZ_32BYTE)); CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL),(DCS_TT)); SETREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE | DCS_NDES); }
//////////////////////////////////////////////////// // 功能: 延迟N个豪秒 // 输入: // 输出: // 返回: // 说明: //////////////////////////////////////////////////// static void dma_start(unsigned int channel, unsigned int srcAddr, unsigned int dstAddr, unsigned int count, unsigned char mode) { #ifdef KPRINTF_DEF kprintf("dma channle = %d\n",channel); kprintf("source = %x, destion = %x, count = %x\n",srcAddr,dstAddr,count*16); #endif OUTREG32(A_DMA_DSA(channel), srcAddr); // DMA数据地址 OUTREG32(A_DMA_DTA(channel), dstAddr); // DMA目标地址 OUTREG32(A_DMA_DTC(channel), count / 16); // 传送DMA的数据组数,当前设置1组为16个数据 SETREG32(A_DMA_DCS(channel), DCS_CTE); // 开始DMA数据传送 //判断是否允许DMA中断 if( mode ) InterruptUnmask(IRQ_DMA_0 + channel, 0); // 允许DMA结束后,自动产生中断 }
//////////////////////////////////////////////////// // 功能: 读取DMA状态 // 输入: // 输出: // 返回: // 说明: //////////////////////////////////////////////////// void GetDmaInfo() { unsigned int channel; channel = PLAYBACK_CHANNEL; for(channel= 0; channel < 4 ; channel++) { kprintf("DMA CHANNEL = %d\n",channel); kprintf("status = %x, count = %x\n",INREG32(A_DMA_DCM(channel)),INREG32(A_DMA_DTC(channel))); kprintf("control = %x,irq = %x\n",INREG32(A_DMA_DCS(channel)),INREG32(A_DMA_DIRQP(channel/6))); kprintf("source addr = %x, destion addr = %x\n",INREG32(A_DMA_DSA(channel)),INREG32(A_DMA_DTA(channel))); kprintf("DRT = %x, DMAC = %x, DCKE = %x\n",INREG32(A_DMA_DRT(channel)),INREG32(A_DMA_DMAC(0)),INREG32(A_DMA_DCKE(0))); } kprintf("\nDMA interrupt count = %d\n",interrupt_count); kprintf("aic register = %x\n",INREG32(A_CPM_CLKGR)); kprintf("dma register = %x\n\n",INREG32(INTC_IMR)); kprintf("======== aic status ========\n"); kprintf("AIC I2S/MSB-justified Control Register I2SCR = %x\n",REG_AIC_I2SCR); kprintf("AIC Controller FIFO Status Register AICSR = %x\n",REG_AIC_SR); kprintf("AIC AC-link Status Register ACSR = %x\n",REG_AIC_ACSR); kprintf("AIC I2S/MSB-justified Status Register I2SSR = %x\n\n",REG_AIC_I2SSR); kprintf("======== codec status ========\n"); kprintf("Audio Interface Control, Software Write = %x\n",codec_reg_read(A_CODEC_AICR)); kprintf("Control Register 1 = %x\n",codec_reg_read(A_CODEC_CR1)); kprintf("Control Register 2 = %x\n",codec_reg_read(A_CODEC_CR2)); kprintf("Control Clock Register 1 = %x\n",codec_reg_read(A_CODEC_CCR1)); kprintf("Control Clock Register 2 = %x\n",codec_reg_read(A_CODEC_CCR2)); kprintf("Power Mode Register 1 = %x\n",codec_reg_read(A_CODEC_PMR1)); kprintf("Power Mode Register 2 = %x\n",codec_reg_read(A_CODEC_PMR2)); kprintf("Control Ramp Register = %x\n",codec_reg_read(A_CODEC_CRR)); kprintf("Interrupt Control Register = %x\n",codec_reg_read(A_CODEC_ICR)); kprintf("Interrupt Flag Register = %x\n",codec_reg_read(A_CODEC_IFR)); kprintf("Control Gain Register 1 = %x\n",codec_reg_read(A_CODEC_CGR1)); kprintf("Control Gain Register 2 = %x\n",codec_reg_read(A_CODEC_CGR2)); kprintf("Control Gain Register 3 = %x\n",codec_reg_read(A_CODEC_CGR3)); kprintf("Control Gain Register 4 = %x\n",codec_reg_read(A_CODEC_CGR4)); kprintf("Control Gain Register 5 = %x\n",codec_reg_read(A_CODEC_CGR5)); kprintf("Control Gain Register 6 = %x\n",codec_reg_read(A_CODEC_CGR6)); kprintf("Control Gain Register 7 = %x\n",codec_reg_read(A_CODEC_CGR7)); kprintf("Control Gain Register 8 = %x\n",codec_reg_read(A_CODEC_CGR8)); kprintf("Control Gain Register 9 = %x\n",codec_reg_read(A_CODEC_CGR9)); kprintf("Control Gain Register 10 = %x\n",codec_reg_read(A_CODEC_CGR10)); }
void dma_nand_set_wait(void *tar,unsigned char src,unsigned int size) { unsigned int setdata[16]; unsigned int *ptemp; ptemp = (unsigned int *)UNCACHE(((unsigned int)(&setdata)+ 31)& (~31)); *ptemp = (unsigned int) ((src << 24) | (src << 16) | (src << 8) | src); if(((unsigned int)tar < 0xa0000000) && size) dma_cache_wback_inv((unsigned long)tar, size); CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE); OUTREG32(A_DMA_DSA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)ptemp)); OUTREG32(A_DMA_DTA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)tar)); OUTREG32(A_DMA_DTC(DMA_NAND_COPY_CHANNEL), size / 32); OUTREG32(A_DMA_DRT(DMA_NAND_COPY_CHANNEL), DRT_AUTO); OUTREG32(A_DMA_DCM(DMA_NAND_COPY_CHANNEL),(DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT| DCM_TSZ_32BYTE)); CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL),(DCS_TT)); SETREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE | DCS_NDES); while (!(INREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL)) & DCS_TT)); }
void dma_nand_copy_wait(void *tar,void *src,int size) { int timeout = 0x1000000; if(((unsigned int)src < 0xa0000000) && size) dma_cache_wback_inv((unsigned long)src, size); if(((unsigned int)tar < 0xa0000000) && size) dma_cache_wback_inv((unsigned long)tar, size); CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE); OUTREG32(A_DMA_DSA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)src)); OUTREG32(A_DMA_DTA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)tar)); OUTREG32(A_DMA_DTC(DMA_NAND_COPY_CHANNEL), size / 32); OUTREG32(A_DMA_DRT(DMA_NAND_COPY_CHANNEL), DRT_AUTO); OUTREG32(A_DMA_DCM(DMA_NAND_COPY_CHANNEL), (DCM_SAI| DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT | DCM_TSZ_32BYTE)); CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL),(DCS_TT)); SETREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE | DCS_NDES); while ((!(INREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL)) & DCS_TT)) && (timeout--)); }
void yuv_copy_nowait_init() { int i; g_desc=(unsigned int*)(((unsigned int)(g_des_space)) | 0xa0000000); for(i = 0;i < 3;i++) { g_desc[i * 8 + 0] = (DES_DAI | DES_SAI | DES_SP_32BIT | DES_DP_32BIT | DES_TSZ_32BIT | DCD_STRIDE_EN | DES_LINK_EN); g_desc[i * 8 + 5] = DRT_AUTO; } g_desc[(--i) * 8 + 0] &= ~(DES_LINK_EN); CLRREG32(A_CPM_CLKGR, ( 1 << 12 )); SETREG32(A_DMA_DMAC(DMA_STRIDE_CPY_CHANNEL / 6),DMAC_DMA_EN); OUTREG32(A_DMA_DCKE(DMA_STRIDE_CPY_CHANNEL / 6),(1 << (DMA_STRIDE_CPY_CHANNEL % 6)));//Open channel clock CLRREG32(A_DMA_DMAC(DMA_STRIDE_CPY_CHANNEL / 6), (DMAC_HALT | DMAC_ADDR_ERR));//Ensure DMAC.AR = 0,DMAC.HLT = 0 CLRREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_AR | DCS_HLT | DCS_TT | DCS_INV); // Ensure DCSn.AR = 0, DCSn.HLT = 0, DCSn.TT = 0, DCSn.INV = 0 OUTREG32(A_DMA_DTC(DMA_STRIDE_CPY_CHANNEL), 0);//DTCn = 0 CLRREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_CTE); CLRREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_NDES); SETREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_DES8); }