static void
AeHardwareInterfaces (
void)
{
ACPI_STATUS Status;
UINT32 Value;
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, 1);
AE_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_GLOBAL_LOCK_ENABLE, 1);
AE_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_SLEEP_ENABLE, 1);
AE_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_ARB_DISABLE, 1);
AE_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &Value);
AE_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_GLOBAL_LOCK_ENABLE, &Value);
AE_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_SLEEP_ENABLE, &Value);
AE_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_ARB_DISABLE, &Value);
AE_CHECK_OK (AcpiReadBitRegister, Status);
}
static ACPI_STATUS
AcpiEvFixedEventInitialize (
void)
{
UINT32 i;
ACPI_STATUS Status;
/*
* Initialize the structure that keeps track of fixed event handlers and
* enable the fixed events.
*/
for (i = 0; i < ACPI_NUM_FIXED_EVENTS; i++)
{
AcpiGbl_FixedEventHandlers[i].Handler = NULL;
AcpiGbl_FixedEventHandlers[i].Context = NULL;
/* Disable the fixed event */
if (AcpiGbl_FixedEventInfo[i].EnableRegisterId != 0xFF)
{
Status = AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[i].EnableRegisterId,
ACPI_DISABLE_EVENT);
if (ACPI_FAILURE (Status))
{
return (Status);
}
}
}
return (AE_OK);
}
ACPI_STATUS
AcpiClearEvent (
UINT32 Event)
{
ACPI_STATUS Status = AE_OK;
ACPI_FUNCTION_TRACE (AcpiClearEvent);
/* Decode the Fixed Event */
if (Event > ACPI_EVENT_MAX)
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/*
* Clear the requested fixed event (By writing a one to the status
* register bit)
*/
Status = AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[Event].StatusRegisterId,
ACPI_CLEAR_STATUS);
return_ACPI_STATUS (Status);
}
static void
acpi_cst_c3_bm_rld_handler(struct cpuhelper_msg *msg)
{
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
cpuhelper_replymsg(msg, 0);
}
ACPI_STATUS
AcpiEnterSleepStateS4bios (
void)
{
UINT32 InValue;
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (AcpiEnterSleepStateS4bios);
/* Clear the wake status bit (PM1) */
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, ACPI_CLEAR_STATUS);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
Status = AcpiHwClearAcpiStatus ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/*
* 1) Disable/Clear all GPEs
* 2) Enable all wakeup GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = FALSE;
Status = AcpiHwEnableAllWakeupGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
ACPI_FLUSH_CPU_CACHE ();
Status = AcpiHwWritePort (AcpiGbl_FADT.SmiCommand,
(UINT32) AcpiGbl_FADT.S4BiosRequest, 8);
do {
AcpiOsStall (ACPI_USEC_PER_MSEC);
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &InValue);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
} while (!InValue);
return_ACPI_STATUS (AE_OK);
}
static void
acpi_cst_c3_bm_rld_handler(netmsg_t msg)
{
struct netmsg_acpi_cst *rmsg = (struct netmsg_acpi_cst *)msg;
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
lwkt_replymsg(&rmsg->base.lmsg, 0);
}
static void
AeHardwareInterfaces (
void)
{
#if (!ACPI_REDUCED_HARDWARE)
ACPI_STATUS Status;
UINT32 Value;
/* If Hardware Reduced flag is set, we are all done */
if (AcpiGbl_ReducedHardware)
{
return;
}
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, 1);
ACPI_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_GLOBAL_LOCK_ENABLE, 1);
ACPI_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_SLEEP_ENABLE, 1);
ACPI_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_ARB_DISABLE, 1);
ACPI_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &Value);
ACPI_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_GLOBAL_LOCK_ENABLE, &Value);
ACPI_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_SLEEP_ENABLE, &Value);
ACPI_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_ARB_DISABLE, &Value);
ACPI_CHECK_OK (AcpiReadBitRegister, Status);
#endif /* !ACPI_REDUCED_HARDWARE */
}
ACPI_STATUS
AcpiEnableEvent (
UINT32 Event,
UINT32 Flags)
{
ACPI_STATUS Status = AE_OK;
UINT32 Value;
ACPI_FUNCTION_TRACE (AcpiEnableEvent);
/* If Hardware Reduced flag is set, there are no fixed events */
if (AcpiGbl_ReducedHardware)
{
return_ACPI_STATUS (AE_OK);
}
/* Decode the Fixed Event */
if (Event > ACPI_EVENT_MAX)
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/*
* Enable the requested fixed event (by writing a one to the enable
* register bit)
*/
Status = AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId,
ACPI_ENABLE_EVENT);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Make sure that the hardware responded */
Status = AcpiReadBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId, &Value);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (Value != 1)
{
ACPI_ERROR ((AE_INFO,
"Could not enable %s event", AcpiUtGetEventName (Event)));
return_ACPI_STATUS (AE_NO_HARDWARE_RESPONSE);
}
return_ACPI_STATUS (Status);
}
static bool
acpicpu_cstate_bm_check(void)
{
uint32_t val = 0;
ACPI_STATUS rv;
rv = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &val);
if (ACPI_FAILURE(rv) || val == 0)
return false;
(void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
return true;
}
static UINT32
AcpiEvFixedEventDispatch (
UINT32 Event)
{
ACPI_FUNCTION_ENTRY ();
/* Clear the status bit */
(void) AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[Event].StatusRegisterId,
ACPI_CLEAR_STATUS);
/*
* Make sure that a handler exists. If not, report an error
* and disable the event to prevent further interrupts.
*/
if (!AcpiGbl_FixedEventHandlers[Event].Handler)
{
(void) AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId,
ACPI_DISABLE_EVENT);
ACPI_ERROR ((AE_INFO,
"No installed handler for fixed event - %s (%u), disabling",
AcpiUtGetEventName (Event), Event));
return (ACPI_INTERRUPT_NOT_HANDLED);
}
/* Invoke the Fixed Event handler */
return ((AcpiGbl_FixedEventHandlers[Event].Handler)(
AcpiGbl_FixedEventHandlers[Event].Context));
}
static UINT32
AcpiEvFixedEventDispatch (
UINT32 Event)
{
ACPI_FUNCTION_ENTRY ();
/* Clear the status bit */
(void) AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[Event].StatusRegisterId,
ACPI_CLEAR_STATUS);
/*
* Make sure we've got a handler. If not, report an error. The event is
* disabled to prevent further interrupts.
*/
if (NULL == AcpiGbl_FixedEventHandlers[Event].Handler)
{
(void) AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId,
ACPI_DISABLE_EVENT);
ACPI_ERROR ((AE_INFO,
"No installed handler for fixed event [0x%08X]",
Event));
return (ACPI_INTERRUPT_NOT_HANDLED);
}
/* Invoke the Fixed Event handler */
return ((AcpiGbl_FixedEventHandlers[Event].Handler)(
AcpiGbl_FixedEventHandlers[Event].Context));
}
ACPI_STATUS
AcpiDisableEvent (
UINT32 Event,
UINT32 Flags)
{
ACPI_STATUS Status = AE_OK;
UINT32 Value;
ACPI_FUNCTION_TRACE (AcpiDisableEvent);
/* Decode the Fixed Event */
if (Event > ACPI_EVENT_MAX)
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/*
* Disable the requested fixed event (by writing a zero to the enable
* register bit)
*/
Status = AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId,
ACPI_DISABLE_EVENT);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
Status = AcpiReadBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId, &Value);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (Value != 0)
{
ACPI_ERROR ((AE_INFO,
"Could not disable %s events", AcpiUtGetEventName (Event)));
return_ACPI_STATUS (AE_NO_HARDWARE_RESPONSE);
}
return_ACPI_STATUS (Status);
}
ACPI_STATUS
AcpiEvReleaseGlobalLock (
void)
{
BOOLEAN Pending = FALSE;
ACPI_STATUS Status = AE_OK;
ACPI_FUNCTION_TRACE (EvReleaseGlobalLock);
/* Lock must be already acquired */
if (!AcpiGbl_GlobalLockAcquired)
{
ACPI_WARNING ((AE_INFO,
"Cannot release the ACPI Global Lock, it has not been acquired"));
return_ACPI_STATUS (AE_NOT_ACQUIRED);
}
if (AcpiGbl_GlobalLockPresent)
{
/* Allow any thread to release the lock */
ACPI_RELEASE_GLOBAL_LOCK (AcpiGbl_FACS, Pending);
/*
* If the pending bit was set, we must write GBL_RLS to the control
* register
*/
if (Pending)
{
Status = AcpiWriteBitRegister (
ACPI_BITREG_GLOBAL_LOCK_RELEASE, ACPI_ENABLE_EVENT);
}
ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Released hardware Global Lock\n"));
}
AcpiGbl_GlobalLockAcquired = FALSE;
/* Release the local GL mutex */
AcpiOsReleaseMutex (AcpiGbl_GlobalLockMutex->Mutex.OsMutex);
return_ACPI_STATUS (Status);
}
/*
* Parse a _CST package and set up its Cx states. Since the _CST object
* can change dynamically, our notify handler may call this function
* to clean up and probe the new _CST package.
*/
static int
acpi_cst_cx_probe_cst(struct acpi_cst_softc *sc, int reprobe)
{
struct acpi_cst_cx *cx_ptr;
ACPI_STATUS status;
ACPI_BUFFER buf;
ACPI_OBJECT *top;
ACPI_OBJECT *pkg;
uint32_t count;
int i;
ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
#ifdef INVARIANTS
if (reprobe)
KKASSERT(&curthread->td_msgport == netisr_cpuport(sc->cst_cpuid));
#endif
buf.Pointer = NULL;
buf.Length = ACPI_ALLOCATE_BUFFER;
status = AcpiEvaluateObject(sc->cst_handle, "_CST", NULL, &buf);
if (ACPI_FAILURE(status))
return (ENXIO);
/* _CST is a package with a count and at least one Cx package. */
top = (ACPI_OBJECT *)buf.Pointer;
if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) {
device_printf(sc->cst_dev, "invalid _CST package\n");
AcpiOsFree(buf.Pointer);
return (ENXIO);
}
if (count != top->Package.Count - 1) {
device_printf(sc->cst_dev, "invalid _CST state count (%d != %d)\n",
count, top->Package.Count - 1);
count = top->Package.Count - 1;
}
if (count > MAX_CX_STATES) {
device_printf(sc->cst_dev, "_CST has too many states (%d)\n", count);
count = MAX_CX_STATES;
}
sc->cst_flags |= ACPI_CST_FLAG_PROBING | ACPI_CST_FLAG_MATCH_HT;
cpu_sfence();
/*
* Free all previously allocated resources
*
* NOTE: It is needed for _CST reprobing.
*/
acpi_cst_free_resource(sc, 0);
/* Set up all valid states. */
sc->cst_cx_count = 0;
cx_ptr = sc->cst_cx_states;
for (i = 0; i < count; i++) {
int error;
pkg = &top->Package.Elements[i + 1];
if (!ACPI_PKG_VALID(pkg, 4) ||
acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 ||
acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 ||
acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) {
device_printf(sc->cst_dev, "skipping invalid Cx state package\n");
continue;
}
/* Validate the state to see if we should use it. */
switch (cx_ptr->type) {
case ACPI_STATE_C1:
sc->cst_non_c3 = i;
cx_ptr->enter = acpi_cst_c1_halt_enter;
error = acpi_cst_cx_setup(cx_ptr);
if (error)
panic("C1 CST HALT setup failed: %d", error);
if (sc->cst_cx_count != 0) {
/*
* C1 is not the first C-state; something really stupid
* is going on ...
*/
sc->cst_flags &= ~ACPI_CST_FLAG_MATCH_HT;
}
cx_ptr++;
sc->cst_cx_count++;
continue;
case ACPI_STATE_C2:
sc->cst_non_c3 = i;
break;
case ACPI_STATE_C3:
default:
if ((acpi_cst_quirks & ACPI_CST_QUIRK_NO_C3) != 0) {
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"cpu_cst%d: C3[%d] not available.\n",
device_get_unit(sc->cst_dev), i));
continue;
}
break;
}
/*
* Allocate the control register for C2 or C3(+).
*/
KASSERT(cx_ptr->res == NULL, ("still has res"));
acpi_PkgRawGas(pkg, 0, &cx_ptr->gas);
/*
* We match number of C2/C3 for hyperthreads, only if the
* register is "Fixed Hardware", e.g. on most of the Intel
* CPUs. We don't have much to do for the rest of the
* register types.
*/
if (cx_ptr->gas.SpaceId != ACPI_ADR_SPACE_FIXED_HARDWARE)
sc->cst_flags &= ~ACPI_CST_FLAG_MATCH_HT;
cx_ptr->rid = sc->cst_parent->cpu_next_rid;
acpi_bus_alloc_gas(sc->cst_dev, &cx_ptr->res_type, &cx_ptr->rid,
&cx_ptr->gas, &cx_ptr->res, RF_SHAREABLE);
if (cx_ptr->res != NULL) {
sc->cst_parent->cpu_next_rid++;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"cpu_cst%d: Got C%d - %d latency\n",
device_get_unit(sc->cst_dev), cx_ptr->type,
cx_ptr->trans_lat));
cx_ptr->enter = acpi_cst_cx_io_enter;
cx_ptr->btag = rman_get_bustag(cx_ptr->res);
cx_ptr->bhand = rman_get_bushandle(cx_ptr->res);
error = acpi_cst_cx_setup(cx_ptr);
if (error)
panic("C%d CST I/O setup failed: %d", cx_ptr->type, error);
cx_ptr++;
sc->cst_cx_count++;
} else {
error = acpi_cst_cx_setup(cx_ptr);
if (!error) {
KASSERT(cx_ptr->enter != NULL,
("C%d enter is not set", cx_ptr->type));
cx_ptr++;
sc->cst_cx_count++;
}
}
}
AcpiOsFree(buf.Pointer);
if (sc->cst_flags & ACPI_CST_FLAG_MATCH_HT) {
cpumask_t mask;
mask = get_cpumask_from_level(sc->cst_cpuid, CORE_LEVEL);
if (CPUMASK_TESTNZERO(mask)) {
int cpu;
for (cpu = 0; cpu < ncpus; ++cpu) {
struct acpi_cst_softc *sc1 = acpi_cst_softc[cpu];
if (sc1 == NULL || sc1 == sc ||
(sc1->cst_flags & ACPI_CST_FLAG_ATTACHED) == 0 ||
(sc1->cst_flags & ACPI_CST_FLAG_MATCH_HT) == 0)
continue;
if (!CPUMASK_TESTBIT(mask, sc1->cst_cpuid))
continue;
if (sc1->cst_cx_count != sc->cst_cx_count) {
struct acpi_cst_softc *src_sc, *dst_sc;
if (bootverbose) {
device_printf(sc->cst_dev,
"inconstent C-state count: %d, %s has %d\n",
sc->cst_cx_count,
device_get_nameunit(sc1->cst_dev),
sc1->cst_cx_count);
}
if (sc1->cst_cx_count > sc->cst_cx_count) {
src_sc = sc1;
dst_sc = sc;
} else {
src_sc = sc;
dst_sc = sc1;
}
acpi_cst_copy(dst_sc, src_sc);
}
}
}
}
if (reprobe) {
/* If there are C3(+) states, always enable bus master wakeup */
if ((acpi_cst_quirks & ACPI_CST_QUIRK_NO_BM) == 0) {
for (i = 0; i < sc->cst_cx_count; ++i) {
struct acpi_cst_cx *cx = &sc->cst_cx_states[i];
if (cx->type >= ACPI_STATE_C3) {
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
break;
}
}
}
/* Fix up the lowest Cx being used */
acpi_cst_set_lowest_oncpu(sc, sc->cst_cx_lowest_req);
}
/*
* Cache the lowest non-C3 state.
* NOTE: must after cst_cx_lowest is set.
*/
acpi_cst_non_c3(sc);
cpu_sfence();
sc->cst_flags &= ~ACPI_CST_FLAG_PROBING;
return (0);
}
/*
* Idle the CPU in the lowest state possible. This function is called with
* interrupts disabled. Note that once it re-enables interrupts, a task
* switch can occur so do not access shared data (i.e. the softc) after
* interrupts are re-enabled.
*/
static void
acpi_cst_idle(void)
{
struct acpi_cst_softc *sc;
struct acpi_cst_cx *cx_next;
union microtime_pcpu start, end;
int cx_next_idx, i, tdiff, bm_arb_disabled = 0;
/* If disabled, return immediately. */
if (acpi_cst_disable_idle) {
ACPI_ENABLE_IRQS();
return;
}
/*
* Look up our CPU id to get our softc. If it's NULL, we'll use C1
* since there is no Cx state for this processor.
*/
sc = acpi_cst_softc[mdcpu->mi.gd_cpuid];
if (sc == NULL) {
acpi_cst_c1_halt();
return;
}
/* Still probing; use C1 */
if (sc->cst_flags & ACPI_CST_FLAG_PROBING) {
acpi_cst_c1_halt();
return;
}
/* Find the lowest state that has small enough latency. */
cx_next_idx = 0;
for (i = sc->cst_cx_lowest; i >= 0; i--) {
if (sc->cst_cx_states[i].trans_lat * 3 <= sc->cst_prev_sleep) {
cx_next_idx = i;
break;
}
}
/*
* Check for bus master activity if needed for the selected state.
* If there was activity, clear the bit and use the lowest non-C3 state.
*/
cx_next = &sc->cst_cx_states[cx_next_idx];
if (cx_next->flags & ACPI_CST_CX_FLAG_BM_STS) {
int bm_active;
AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
if (bm_active != 0) {
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
cx_next_idx = sc->cst_non_c3;
}
}
/* Select the next state and update statistics. */
cx_next = &sc->cst_cx_states[cx_next_idx];
sc->cst_cx_stats[cx_next_idx]++;
KASSERT(cx_next->type != ACPI_STATE_C0, ("C0 sleep"));
/*
* Execute HLT (or equivalent) and wait for an interrupt. We can't
* calculate the time spent in C1 since the place we wake up is an
* ISR. Assume we slept half of quantum and return.
*/
if (cx_next->type == ACPI_STATE_C1) {
sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + 500000 / hz) / 4;
cx_next->enter(cx_next);
return;
}
/* Execute the proper preamble before enter the selected state. */
if (cx_next->preamble == ACPI_CST_CX_PREAMBLE_BM_ARB) {
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
bm_arb_disabled = 1;
} else if (cx_next->preamble == ACPI_CST_CX_PREAMBLE_WBINVD) {
ACPI_FLUSH_CPU_CACHE();
}
/*
* Enter the selected state and check time spent asleep.
*/
microtime_pcpu_get(&start);
cpu_mfence();
cx_next->enter(cx_next);
cpu_mfence();
microtime_pcpu_get(&end);
/* Enable bus master arbitration, if it was disabled. */
if (bm_arb_disabled)
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
ACPI_ENABLE_IRQS();
/* Find the actual time asleep in microseconds. */
tdiff = microtime_pcpu_diff(&start, &end);
sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + tdiff) / 4;
}
status_t
write_bit_register(uint32 regid, uint32 val)
{
return AcpiWriteBitRegister(regid, val);
}
ACPI_STATUS
AcpiLeaveSleepState (
UINT8 SleepState)
{
ACPI_OBJECT_LIST ArgList;
ACPI_OBJECT Arg;
ACPI_STATUS Status;
ACPI_BIT_REGISTER_INFO *SleepTypeRegInfo;
ACPI_BIT_REGISTER_INFO *SleepEnableRegInfo;
UINT32 Pm1aControl;
UINT32 Pm1bControl;
ACPI_FUNCTION_TRACE (AcpiLeaveSleepState);
/*
* Set SLP_TYPE and SLP_EN to state S0.
* This is unclear from the ACPI Spec, but it is required
* by some machines.
*/
Status = AcpiGetSleepTypeData (ACPI_STATE_S0,
&AcpiGbl_SleepTypeA, &AcpiGbl_SleepTypeB);
if (ACPI_SUCCESS (Status))
{
SleepTypeRegInfo =
AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_TYPE);
SleepEnableRegInfo =
AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_ENABLE);
/* Get current value of PM1A control */
Status = AcpiHwRegisterRead (ACPI_REGISTER_PM1_CONTROL,
&Pm1aControl);
if (ACPI_SUCCESS (Status))
{
/* Clear the SLP_EN and SLP_TYP fields */
Pm1aControl &= ~(SleepTypeRegInfo->AccessBitMask |
SleepEnableRegInfo->AccessBitMask);
Pm1bControl = Pm1aControl;
/* Insert the SLP_TYP bits */
Pm1aControl |= (AcpiGbl_SleepTypeA <<
SleepTypeRegInfo->BitPosition);
Pm1bControl |= (AcpiGbl_SleepTypeB <<
SleepTypeRegInfo->BitPosition);
/* Write the control registers and ignore any errors */
(void) AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
}
}
/* Ensure EnterSleepStatePrep -> EnterSleepState ordering */
AcpiGbl_SleepTypeA = ACPI_SLEEP_TYPE_INVALID;
/* Setup parameter object */
ArgList.Count = 1;
ArgList.Pointer = &Arg;
Arg.Type = ACPI_TYPE_INTEGER;
/* Ignore any errors from these methods */
Arg.Integer.Value = ACPI_SST_WAKING;
Status = AcpiEvaluateObject (NULL, METHOD_NAME__SST, &ArgList, NULL);
if (ACPI_FAILURE (Status) && Status != AE_NOT_FOUND)
{
ACPI_EXCEPTION ((AE_INFO, Status, "During Method _SST"));
}
Arg.Integer.Value = SleepState;
Status = AcpiEvaluateObject (NULL, METHOD_NAME__BFS, &ArgList, NULL);
if (ACPI_FAILURE (Status) && Status != AE_NOT_FOUND)
{
ACPI_EXCEPTION ((AE_INFO, Status, "During Method _BFS"));
}
Status = AcpiEvaluateObject (NULL, METHOD_NAME__WAK, &ArgList, NULL);
if (ACPI_FAILURE (Status) && Status != AE_NOT_FOUND)
{
ACPI_EXCEPTION ((AE_INFO, Status, "During Method _WAK"));
}
/* TBD: _WAK "sometimes" returns stuff - do we want to look at it? */
/*
* Restore the GPEs:
* 1) Disable/Clear all GPEs
* 2) Enable all runtime GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = TRUE;
Status = AcpiHwEnableAllRuntimeGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Enable power button */
(void) AcpiWriteBitRegister(
AcpiGbl_FixedEventInfo[ACPI_EVENT_POWER_BUTTON].EnableRegisterId,
ACPI_ENABLE_EVENT);
(void) AcpiWriteBitRegister(
AcpiGbl_FixedEventInfo[ACPI_EVENT_POWER_BUTTON].StatusRegisterId,
ACPI_CLEAR_STATUS);
/*
* Enable BM arbitration. This feature is contained within an
* optional register (PM2 Control), so ignore a BAD_ADDRESS
* exception.
*/
Status = AcpiWriteBitRegister (ACPI_BITREG_ARB_DISABLE, 0);
if (ACPI_FAILURE (Status) && (Status != AE_BAD_ADDRESS))
{
return_ACPI_STATUS (Status);
}
Arg.Integer.Value = ACPI_SST_WORKING;
Status = AcpiEvaluateObject (NULL, METHOD_NAME__SST, &ArgList, NULL);
if (ACPI_FAILURE (Status) && Status != AE_NOT_FOUND)
{
ACPI_EXCEPTION ((AE_INFO, Status, "During Method _SST"));
}
return_ACPI_STATUS (Status);
}
ACPI_STATUS
AcpiHwLegacySleep (
UINT8 SleepState,
UINT8 Flags)
{
ACPI_BIT_REGISTER_INFO *SleepTypeRegInfo;
ACPI_BIT_REGISTER_INFO *SleepEnableRegInfo;
UINT32 Pm1aControl;
UINT32 Pm1bControl;
UINT32 InValue;
UINT32 Retry;
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (HwLegacySleep);
SleepTypeRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_TYPE);
SleepEnableRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_ENABLE);
/* Clear wake status */
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, ACPI_CLEAR_STATUS);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Clear all fixed and general purpose status bits */
Status = AcpiHwClearAcpiStatus ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState != ACPI_STATE_S5)
{
/*
* Disable BM arbitration. This feature is contained within an
* optional register (PM2 Control), so ignore a BAD_ADDRESS
* exception.
*/
Status = AcpiWriteBitRegister (ACPI_BITREG_ARB_DISABLE, 1);
if (ACPI_FAILURE (Status) && (Status != AE_BAD_ADDRESS))
{
return_ACPI_STATUS (Status);
}
}
/*
* 1) Disable/Clear all GPEs
* 2) Enable all wakeup GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = FALSE;
Status = AcpiHwEnableAllWakeupGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Optionally execute _GTS (Going To Sleep) */
if (Flags & ACPI_EXECUTE_GTS)
{
AcpiHwExecuteSleepMethod (METHOD_PATHNAME__GTS, SleepState);
}
/* Get current value of PM1A control */
Status = AcpiHwRegisterRead (ACPI_REGISTER_PM1_CONTROL,
&Pm1aControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
ACPI_DEBUG_PRINT ((ACPI_DB_INIT,
"Entering sleep state [S%u]\n", SleepState));
/* Clear the SLP_EN and SLP_TYP fields */
Pm1aControl &= ~(SleepTypeRegInfo->AccessBitMask |
SleepEnableRegInfo->AccessBitMask);
Pm1bControl = Pm1aControl;
/* Insert the SLP_TYP bits */
Pm1aControl |= (AcpiGbl_SleepTypeA << SleepTypeRegInfo->BitPosition);
Pm1bControl |= (AcpiGbl_SleepTypeB << SleepTypeRegInfo->BitPosition);
/*
* We split the writes of SLP_TYP and SLP_EN to workaround
* poorly implemented hardware.
*/
/* Write #1: write the SLP_TYP data to the PM1 Control registers */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Insert the sleep enable (SLP_EN) bit */
Pm1aControl |= SleepEnableRegInfo->AccessBitMask;
Pm1bControl |= SleepEnableRegInfo->AccessBitMask;
/* Flush caches, as per ACPI specification */
ACPI_FLUSH_CPU_CACHE ();
/* Write #2: Write both SLP_TYP + SLP_EN */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState > ACPI_STATE_S3)
{
/*
* We wanted to sleep > S3, but it didn't happen (by virtue of the
* fact that we are still executing!)
*
* Wait ten seconds, then try again. This is to get S4/S5 to work on
* all machines.
*
* We wait so long to allow chipsets that poll this reg very slowly
* to still read the right value. Ideally, this block would go
* away entirely.
*/
AcpiOsStall (10000000);
Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_CONTROL,
SleepEnableRegInfo->AccessBitMask);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
}
/* Wait for transition back to Working State */
Retry = 1000;
do
{
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &InValue);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (AcpiGbl_EnableInterpreterSlack)
{
/*
* Some BIOSs don't set WAK_STS at all. Give up waiting after
* 1000 retries if it still isn't set.
*/
if (Retry-- == 0)
{
break;
}
}
} while (!InValue);
return_ACPI_STATUS (AE_OK);
}
ACPI_STATUS
AcpiEnterSleepState (
UINT8 SleepState)
{
UINT32 Pm1aControl;
UINT32 Pm1bControl;
ACPI_BIT_REGISTER_INFO *SleepTypeRegInfo;
ACPI_BIT_REGISTER_INFO *SleepEnableRegInfo;
UINT32 InValue;
ACPI_OBJECT_LIST ArgList;
ACPI_OBJECT Arg;
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (AcpiEnterSleepState);
if ((AcpiGbl_SleepTypeA > ACPI_SLEEP_TYPE_MAX) ||
(AcpiGbl_SleepTypeB > ACPI_SLEEP_TYPE_MAX))
{
ACPI_ERROR ((AE_INFO, "Sleep values out of range: A=%X B=%X",
AcpiGbl_SleepTypeA, AcpiGbl_SleepTypeB));
return_ACPI_STATUS (AE_AML_OPERAND_VALUE);
}
SleepTypeRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_TYPE);
SleepEnableRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_ENABLE);
/* Clear wake status */
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, ACPI_CLEAR_STATUS);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Clear all fixed and general purpose status bits */
Status = AcpiHwClearAcpiStatus ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState != ACPI_STATE_S5)
{
/*
* Disable BM arbitration. This feature is contained within an
* optional register (PM2 Control), so ignore a BAD_ADDRESS
* exception.
*/
Status = AcpiWriteBitRegister (ACPI_BITREG_ARB_DISABLE, 1);
if (ACPI_FAILURE (Status) && (Status != AE_BAD_ADDRESS))
{
return_ACPI_STATUS (Status);
}
}
/*
* 1) Disable/Clear all GPEs
* 2) Enable all wakeup GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = FALSE;
Status = AcpiHwEnableAllWakeupGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Execute the _GTS method (Going To Sleep) */
ArgList.Count = 1;
ArgList.Pointer = &Arg;
Arg.Type = ACPI_TYPE_INTEGER;
Arg.Integer.Value = SleepState;
Status = AcpiEvaluateObject (NULL, METHOD_NAME__GTS, &ArgList, NULL);
if (ACPI_FAILURE (Status) && Status != AE_NOT_FOUND)
{
return_ACPI_STATUS (Status);
}
/* Get current value of PM1A control */
Status = AcpiHwRegisterRead (ACPI_REGISTER_PM1_CONTROL,
&Pm1aControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
ACPI_DEBUG_PRINT ((ACPI_DB_INIT,
"Entering sleep state [S%d]\n", SleepState));
/* Clear the SLP_EN and SLP_TYP fields */
Pm1aControl &= ~(SleepTypeRegInfo->AccessBitMask |
SleepEnableRegInfo->AccessBitMask);
Pm1bControl = Pm1aControl;
/* Insert the SLP_TYP bits */
Pm1aControl |= (AcpiGbl_SleepTypeA << SleepTypeRegInfo->BitPosition);
Pm1bControl |= (AcpiGbl_SleepTypeB << SleepTypeRegInfo->BitPosition);
/*
* We split the writes of SLP_TYP and SLP_EN to workaround
* poorly implemented hardware.
*/
/* Write #1: write the SLP_TYP data to the PM1 Control registers */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Insert the sleep enable (SLP_EN) bit */
Pm1aControl |= SleepEnableRegInfo->AccessBitMask;
Pm1bControl |= SleepEnableRegInfo->AccessBitMask;
/* Flush caches, as per ACPI specification */
ACPI_FLUSH_CPU_CACHE ();
/* Write #2: Write both SLP_TYP + SLP_EN */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState > ACPI_STATE_S3)
{
/*
* We wanted to sleep > S3, but it didn't happen (by virtue of the
* fact that we are still executing!)
*
* Wait ten seconds, then try again. This is to get S4/S5 to work on
* all machines.
*
* We wait so long to allow chipsets that poll this reg very slowly
* to still read the right value. Ideally, this block would go
* away entirely.
*/
AcpiOsStall (10000000);
Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_CONTROL,
SleepEnableRegInfo->AccessBitMask);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
}
/* Wait until we enter sleep state */
do
{
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &InValue);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Spin until we wake */
} while (!InValue);
return_ACPI_STATUS (AE_OK);
}
static int
acpi_cpu_quirks(void)
{
device_t acpi_dev;
uint32_t val;
ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
/*
* Bus mastering arbitration control is needed to keep caches coherent
* while sleeping in C3. If it's not present but a working flush cache
* instruction is present, flush the caches before entering C3 instead.
* Otherwise, just disable C3 completely.
*/
if (AcpiGbl_FADT.Pm2ControlBlock == 0 ||
AcpiGbl_FADT.Pm2ControlLength == 0) {
if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) &&
(AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) {
cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: no BM control, using flush cache method\n"));
} else {
cpu_quirks |= CPU_QUIRK_NO_C3;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: no BM control, C3 not available\n"));
}
}
/*
* If we are using generic Cx mode, C3 on multiple CPUs requires using
* the expensive flush cache instruction.
*/
if (cpu_cx_generic && mp_ncpus > 1) {
cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: SMP, using flush cache mode for C3\n"));
}
/* Look for various quirks of the PIIX4 part. */
acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3);
if (acpi_dev != NULL) {
switch (pci_get_revid(acpi_dev)) {
/*
* Disable C3 support for all PIIX4 chipsets. Some of these parts
* do not report the BMIDE status to the BM status register and
* others have a livelock bug if Type-F DMA is enabled. Linux
* works around the BMIDE bug by reading the BM status directly
* but we take the simpler approach of disabling C3 for these
* parts.
*
* See erratum #18 ("C3 Power State/BMIDE and Type-F DMA
* Livelock") from the January 2002 PIIX4 specification update.
* Applies to all PIIX4 models.
*
* Also, make sure that all interrupts cause a "Stop Break"
* event to exit from C2 state.
* Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
* should be set to zero, otherwise it causes C2 to short-sleep.
* PIIX4 doesn't properly support C3 and bus master activity
* need not break out of C2.
*/
case PCI_REVISION_A_STEP:
case PCI_REVISION_B_STEP:
case PCI_REVISION_4E:
case PCI_REVISION_4M:
cpu_quirks |= CPU_QUIRK_NO_C3;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: working around PIIX4 bug, disabling C3\n"));
val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
val |= PIIX4_STOP_BREAK_MASK;
pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
}
AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
if (val) {
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
}
break;
default:
break;
}
}
return (0);
}
/*
* Idle the CPU in the lowest state possible. This function is called with
* interrupts disabled. Note that once it re-enables interrupts, a task
* switch can occur so do not access shared data (i.e. the softc) after
* interrupts are re-enabled.
*/
static void
acpi_cpu_idle()
{
struct acpi_cpu_softc *sc;
struct acpi_cx *cx_next;
uint32_t start_time, end_time;
int bm_active, cx_next_idx, i;
/* If disabled, return immediately. */
if (cpu_disable_idle) {
ACPI_ENABLE_IRQS();
return;
}
/*
* Look up our CPU id to get our softc. If it's NULL, we'll use C1
* since there is no ACPI processor object for this CPU. This occurs
* for logical CPUs in the HTT case.
*/
sc = cpu_softc[PCPU_GET(cpuid)];
if (sc == NULL) {
acpi_cpu_c1();
return;
}
/* Find the lowest state that has small enough latency. */
cx_next_idx = 0;
for (i = sc->cpu_cx_lowest; i >= 0; i--) {
if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) {
cx_next_idx = i;
break;
}
}
/*
* Check for bus master activity. If there was activity, clear
* the bit and use the lowest non-C3 state. Note that the USB
* driver polling for new devices keeps this bit set all the
* time if USB is loaded.
*/
if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
if (bm_active != 0) {
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
cx_next_idx = min(cx_next_idx, sc->cpu_non_c3);
}
}
/* Select the next state and update statistics. */
cx_next = &sc->cpu_cx_states[cx_next_idx];
sc->cpu_cx_stats[cx_next_idx]++;
KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));
/*
* Execute HLT (or equivalent) and wait for an interrupt. We can't
* calculate the time spent in C1 since the place we wake up is an
* ISR. Assume we slept half of quantum and return.
*/
if (cx_next->type == ACPI_STATE_C1) {
sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + 500000 / hz) / 4;
acpi_cpu_c1();
return;
}
/*
* For C3, disable bus master arbitration and enable bus master wake
* if BM control is available, otherwise flush the CPU cache.
*/
if (cx_next->type == ACPI_STATE_C3) {
if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
} else
ACPI_FLUSH_CPU_CACHE();
}
/*
* Read from P_LVLx to enter C2(+), checking time spent asleep.
* Use the ACPI timer for measuring sleep time. Since we need to
* get the time very close to the CPU start/stop clock logic, this
* is the only reliable time source.
*/
AcpiRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock);
CPU_GET_REG(cx_next->p_lvlx, 1);
/*
* Read the end time twice. Since it may take an arbitrary time
* to enter the idle state, the first read may be executed before
* the processor has stopped. Doing it again provides enough
* margin that we are certain to have a correct value.
*/
AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
/* Enable bus master arbitration and disable bus master wakeup. */
if (cx_next->type == ACPI_STATE_C3 &&
(cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
}
ACPI_ENABLE_IRQS();
/* Find the actual time asleep in microseconds. */
end_time = acpi_TimerDelta(end_time, start_time);
sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4;
}
/*
* The main idle loop.
*/
void
acpicpu_cstate_idle(void)
{
struct cpu_info *ci = curcpu();
struct acpicpu_softc *sc;
int state;
KASSERT(acpicpu_sc != NULL);
KASSERT(ci->ci_acpiid < maxcpus);
sc = acpicpu_sc[ci->ci_acpiid];
if (__predict_false(sc == NULL))
return;
KASSERT(ci->ci_ilevel == IPL_NONE);
KASSERT((sc->sc_flags & ACPICPU_FLAG_C) != 0);
if (__predict_false(sc->sc_cold != false))
return;
if (__predict_false(mutex_tryenter(&sc->sc_mtx) == 0))
return;
state = acpicpu_cstate_latency(sc);
mutex_exit(&sc->sc_mtx);
/*
* Apply AMD C1E quirk.
*/
if ((sc->sc_flags & ACPICPU_FLAG_C_C1E) != 0)
acpicpu_md_quirk_c1e();
/*
* Check for bus master activity. Note that particularly usb(4)
* causes high activity, which may prevent the use of C3 states.
*/
if ((sc->sc_cstate[state].cs_flags & ACPICPU_FLAG_C_BM_STS) != 0) {
if (acpicpu_cstate_bm_check() != false)
state--;
if (__predict_false(sc->sc_cstate[state].cs_method == 0))
state = ACPI_STATE_C1;
}
KASSERT(state != ACPI_STATE_C0);
if (state != ACPI_STATE_C3) {
acpicpu_cstate_idle_enter(sc, state);
return;
}
/*
* On all recent (Intel) CPUs caches are shared
* by CPUs and bus master control is required to
* keep these coherent while in C3. Flushing the
* CPU caches is only the last resort.
*/
if ((sc->sc_flags & ACPICPU_FLAG_C_BM) == 0)
ACPI_FLUSH_CPU_CACHE();
/*
* Allow the bus master to request that any given
* CPU should return immediately to C0 from C3.
*/
if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0)
(void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
/*
* It may be necessary to disable bus master arbitration
* to ensure that bus master cycles do not occur while
* sleeping in C3 (see ACPI 4.0, section 8.1.4).
*/
if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0)
(void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
acpicpu_cstate_idle_enter(sc, state);
/*
* Disable bus master wake and re-enable the arbiter.
*/
if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0)
(void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0)
(void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
}
ACPI_STATUS
AcpiHwLegacySleep (
UINT8 SleepState)
{
ACPI_BIT_REGISTER_INFO *SleepTypeRegInfo;
ACPI_BIT_REGISTER_INFO *SleepEnableRegInfo;
UINT32 Pm1aControl;
UINT32 Pm1bControl;
UINT32 InValue;
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (HwLegacySleep);
SleepTypeRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_TYPE);
SleepEnableRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_ENABLE);
/* Clear wake status */
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, ACPI_CLEAR_STATUS);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Clear all fixed and general purpose status bits */
Status = AcpiHwClearAcpiStatus ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/*
* 1) Disable/Clear all GPEs
* 2) Enable all wakeup GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = FALSE;
Status = AcpiHwEnableAllWakeupGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Get current value of PM1A control */
Status = AcpiHwRegisterRead (ACPI_REGISTER_PM1_CONTROL,
&Pm1aControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
ACPI_DEBUG_PRINT ((ACPI_DB_INIT,
"Entering sleep state [S%u]\n", SleepState));
/* Clear the SLP_EN and SLP_TYP fields */
Pm1aControl &= ~(SleepTypeRegInfo->AccessBitMask |
SleepEnableRegInfo->AccessBitMask);
Pm1bControl = Pm1aControl;
/* Insert the SLP_TYP bits */
Pm1aControl |= (AcpiGbl_SleepTypeA << SleepTypeRegInfo->BitPosition);
Pm1bControl |= (AcpiGbl_SleepTypeB << SleepTypeRegInfo->BitPosition);
/*
* We split the writes of SLP_TYP and SLP_EN to workaround
* poorly implemented hardware.
*/
/* Write #1: write the SLP_TYP data to the PM1 Control registers */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Insert the sleep enable (SLP_EN) bit */
Pm1aControl |= SleepEnableRegInfo->AccessBitMask;
Pm1bControl |= SleepEnableRegInfo->AccessBitMask;
/* Flush caches, as per ACPI specification */
ACPI_FLUSH_CPU_CACHE ();
/* Write #2: Write both SLP_TYP + SLP_EN */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState > ACPI_STATE_S3)
{
/*
* We wanted to sleep > S3, but it didn't happen (by virtue of the
* fact that we are still executing!)
*
* Wait ten seconds, then try again. This is to get S4/S5 to work on
* all machines.
*
* We wait so long to allow chipsets that poll this reg very slowly
* to still read the right value. Ideally, this block would go
* away entirely.
*/
AcpiOsStall (10 * ACPI_USEC_PER_SEC);
Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_CONTROL,
SleepEnableRegInfo->AccessBitMask);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
}
/* Wait for transition back to Working State */
do
{
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &InValue);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
} while (!InValue);
return_ACPI_STATUS (AE_OK);
}
ACPI_STATUS
AcpiHwLegacyWake (
UINT8 SleepState)
{
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (HwLegacyWake);
/* Ensure EnterSleepStatePrep -> EnterSleepState ordering */
AcpiGbl_SleepTypeA = ACPI_SLEEP_TYPE_INVALID;
AcpiHwExecuteSleepMethod (__UNCONST(METHOD_PATHNAME__SST), ACPI_SST_WAKING);
/*
* GPEs must be enabled before _WAK is called as GPEs
* might get fired there
*
* Restore the GPEs:
* 1) Disable/Clear all GPEs
* 2) Enable all runtime GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
Status = AcpiHwEnableAllRuntimeGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/*
* Now we can execute _WAK, etc. Some machines require that the GPEs
* are enabled before the wake methods are executed.
*/
AcpiHwExecuteSleepMethod (__UNCONST(METHOD_PATHNAME__WAK), SleepState);
/*
* Some BIOS code assumes that WAK_STS will be cleared on resume
* and use it to determine whether the system is rebooting or
* resuming. Clear WAK_STS for compatibility.
*/
(void) AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, ACPI_CLEAR_STATUS);
AcpiGbl_SystemAwakeAndRunning = TRUE;
/* Enable power button */
(void) AcpiWriteBitRegister(
AcpiGbl_FixedEventInfo[ACPI_EVENT_POWER_BUTTON].EnableRegisterId,
ACPI_ENABLE_EVENT);
(void) AcpiWriteBitRegister(
AcpiGbl_FixedEventInfo[ACPI_EVENT_POWER_BUTTON].StatusRegisterId,
ACPI_CLEAR_STATUS);
AcpiHwExecuteSleepMethod (__UNCONST(METHOD_PATHNAME__SST), ACPI_SST_WORKING);
return_ACPI_STATUS (Status);
}
void start() {
ACPI_STATUS status = AE_OK;
printf("acpica: starting...\n");
// NB! Must be at least as large as physical memory - the ACPI tables could
// be anywhere. (Could be handled by AcpiOsMapMemory though.)
map(0, MAP_PHYS | PROT_READ | PROT_WRITE | PROT_NO_CACHE,
(void*)ACPI_PHYS_BASE, 0, USER_MAP_MAX - ACPI_PHYS_BASE);
__default_section_init();
AcpiDbgLayer = 0;
AcpiDbgLevel = ACPI_LV_REPAIR | ACPI_LV_INTERRUPTS;
status = InitializeFullAcpi ();
CHECK_STATUS("InitializeFullAcpi");
int pic_mode = 0; // Default is PIC mode if something fails
status = PrintAPICTable();
CHECK_STATUS("PrintAPICTable");
status = FindIOAPICs(&pic_mode);
CHECK_STATUS("Find IOAPIC");
status = ExecuteOSI(pic_mode);
CHECK_STATUS("ExecuteOSI");
// Tables we get in Bochs:
// * DSDT: All the AML code
// * FACS
// * FACP
// * APIC (= MADT)
// * SSDT: Secondary System Description Table
// Contains more AML code loaded automatically by ACPICA
// More tables on qemu:
// * Another SSDT (Loaded by ACPICA)
// * HPET table
// PrintFACSTable();
// PrintFACPTable();
// TODO Iterate through and disable all pci interrupt link devices (call
// _DIS). Then we'll enable the ones we actually intend to use.
EnumeratePCI();
AcpiWriteBitRegister(ACPI_BITREG_SCI_ENABLE, 1);
//AcpiWriteBitRegister(ACPI_BITREG_POWER_BUTTON_ENABLE, 1);
AcpiInstallGlobalEventHandler(GlobalEventHandler, NULL);
AcpiEnableEvent(ACPI_EVENT_POWER_BUTTON, 0);
for (;;) {
ipc_dest_t rcpt = 0x100;
ipc_arg_t arg = 0;
ipc_arg_t arg2 = 0;
ipc_msg_t msg = recv2(&rcpt, &arg, &arg2);
//printf("acpica: Received %#lx from %#lx: %#lx %#lx\n", msg, rcpt, arg, arg2);
if (msg == MSG_PULSE) {
if (AcpiOsCheckInterrupt(rcpt, arg)) {
continue;
} else {
printf("acpica: Unhandled pulse: %#x from %#lx\n", arg, rcpt);
}
}
switch (msg & 0xff)
{
case MSG_ACPI_FIND_PCI:
MsgFindPci(rcpt, arg);
break;
case MSG_ACPI_CLAIM_PCI:
MsgClaimPci(rcpt, arg, arg2);
break;
// This feels a bit wrong, but as long as we use PIO access to PCI
// configuration space, we need to serialize all accesses.
case MSG_ACPI_READ_PCI:
arg = PciReadWord((arg & 0x7ffffffc) | 0x80000000);
send1(MSG_ACPI_READ_PCI, rcpt, arg);
break;
case MSG_ACPI_DEBUGGER_INIT:
debugger_pre_cmd();
send0(MSG_ACPI_DEBUGGER_INIT, rcpt);
break;
case MSG_ACPI_DEBUGGER_BUFFER:
assert(debugger_buffer_pos < ACPI_DB_LINE_BUFFER_SIZE);
AcpiGbl_DbLineBuf[debugger_buffer_pos++] = arg;
send0(MSG_ACPI_DEBUGGER_BUFFER, rcpt);
break;
case MSG_ACPI_DEBUGGER_CMD:
assert(debugger_buffer_pos < ACPI_DB_LINE_BUFFER_SIZE);
AcpiGbl_DbLineBuf[debugger_buffer_pos++] = 0;
putchar('\n');
AcpiDbCommandDispatch(AcpiGbl_DbLineBuf, NULL, NULL);
debugger_pre_cmd();
send0(MSG_ACPI_DEBUGGER_CMD, rcpt);
break;
case MSG_ACPI_DEBUGGER_CLR_BUFFER:
debugger_pre_cmd();
send0(MSG_ACPI_DEBUGGER_CLR_BUFFER, rcpt);
break;
case MSG_REG_IRQ:
RegIRQ(rcpt, arg);
continue;
case MSG_IRQ_ACK:
AckIRQ(rcpt);
continue;
}
// TODO Handle other stuff.
if (rcpt == 0x100)
{
hmod(rcpt, 0, 0);
}
}
__builtin_unreachable();
failed:
printf("ACPI failed :( (status %x)\n", status);
abort();
}
