void Speaker_ClassD_Open(void)
{
kal_uint32 i, SPKTrimReg = 0;
pr_warn("%s\n", __func__);
/* spk trim */
Ana_Set_Reg(SPK_CON7, 0x4531, 0xffff); /* TD1,TD2,TD3 for trim (related with trim waiting time) */
Ana_Set_Reg(SPK_CON0, 0x3008, 0xffff); /* Set to class D mode, set 0dB amplifier gain, enable trim function */
Ana_Set_Reg(SPK_CON13, 0x1800, 0xffff); /* Offset trim RSV bit */
Ana_Set_Reg(SPK_CON2, 0x04A4, 0xffff); /* Turn on OC function, set SPK PGA in DCC mod */
Ana_Set_Reg(SPK_ANA_CON0, 0x5000, 0xffff); /* Set 12dB PGA gain */
Ana_Set_Reg(SPK_CON9, 0x2000, 0xffff); /* Set Fast Vcm mode */
Ana_Set_Reg(SPK_CON0, 0x3009, 0xffff); /* Turn on speaker */
Ana_Set_Reg(SPK_CON9, 0x0A00, 0xffff); /* Set Vcm high PSRR mode */
for (i = 0; i < 10; i++)
udelay(1000); /* wait 10ms for trimming */
Ana_Set_Reg(SPK_CON0, 0x3001, 0xffff); /* Turn off trim,(set to class D mode) */
Ana_Set_Reg(SPK_CON13, 0x0000, 0xffff); /* Clock from Saw-tooth to Triangular wave */
SPKTrimReg = Ana_Get_Reg(SPK_CON1);
if ((SPKTrimReg & 0x8000) == 0)
pr_warn("spk trim fail!\n");
else
pr_warn("spk trim offset=%d\n", (SPKTrimReg & 0x1f));
/* spk amp gain fixed at 0dB */
Ana_Set_Reg(SPK_CON0, 0x3001, 0xffff); /* set 0dB amplifier gain */
}
void Speaker_ClassD_Open(void)
{
kal_uint32 i, SPKTrimReg = 0;
printk("%s\n", __func__);
// spk trim
Ana_Set_Reg(SPK_CON7, 0x4531, 0xffff); //TD1,TD2,TD3 for trim (related with trim waiting time)
Ana_Set_Reg(SPK_CON0, 0x3008, 0xffff);//Set to class D mode, set 0dB amplifier gain, enable trim function
Ana_Set_Reg(SPK_CON13, 0x1800, 0xffff);//Offset trim RSV bit
Ana_Set_Reg(SPK_CON2, 0x04A4, 0xffff); //Turn on OC function, set SPK PGA in DCC mod
Ana_Set_Reg(SPK_ANA_CON0, 0x5000, 0xffff); //Set 12dB PGA gain
Ana_Set_Reg(SPK_CON9, 0x2000, 0xffff); //Set Fast Vcm mode
Ana_Set_Reg(SPK_CON0, 0x3009, 0xffff); //Turn on speaker
Ana_Set_Reg(SPK_CON9, 0x0A00, 0xffff); //Set Vcm high PSRR mode
for (i = 0; i < 10; i++)
{
udelay(1000); //wait 10ms for trimming
}
Ana_Set_Reg(SPK_CON0, 0x3001, 0xffff); //Turn off trim,(set to class D mode)
Ana_Set_Reg(SPK_CON13, 0x0000, 0xffff); //Clock from Saw-tooth to Triangular wave
SPKTrimReg = Ana_Get_Reg(SPK_CON1);
if ((SPKTrimReg & 0x8000) == 0)
{
printk("spk trim fail!\n");
}
else
{
printk("spk trim offset=%d\n", (SPKTrimReg & 0x1f));
}
// spk amp gain fixed at 0dB
Ana_Set_Reg(SPK_CON0, 0x3001, 0xffff); //set 0dB amplifier gain
}
void Ana_Set_Reg(uint32 offset, uint32 value, uint32 mask)
{
// set pmic register or analog CONTROL_IFACE_PATH
int ret = 0;
#ifdef AUDIO_USING_WRAP_DRIVER
uint32 Reg_Value = Ana_Get_Reg(offset);
Reg_Value &= (~mask);
Reg_Value |= (value & mask);
ret = pwrap_write(offset, Reg_Value);
Reg_Value = Ana_Get_Reg(offset);
if ((Reg_Value & mask) != (value & mask))
{
pr_warn("Ana_Set_Reg offset= 0x%x , value = 0x%x mask = 0x%x ret = %d Reg_Value = 0x%x\n",
offset, value, mask, ret, Reg_Value);
}
#endif
}
bool GetSpeakerOcFlag(void)
{
unsigned int OCregister = 0;
unsigned int bitmask = 1;
bool DmodeFlag = false;
bool ABmodeFlag = false;
Ana_Set_Reg(TOP_CKPDN_CON2_CLR, 0x3, 0xffff);
OCregister = Ana_Get_Reg(SPK_CON6);
DmodeFlag = OCregister & (bitmask << 14); // ; no.14 bit is SPK_D_OC_L_DEG
ABmodeFlag = OCregister & (bitmask << 15); // ; no.15 bit is SPK_AB_OC_L_DEG
printk("OCregister = %d \n", OCregister);
return (DmodeFlag | ABmodeFlag);
}
kal_uint32 Ana_Check_Backup_Memory(kal_uint32 offset)
{
kal_uint32 val_1=0, val_2=0, ret_value = 0;
val_1 = Ana_Get_Reg(offset);
val_2 = Ana_Get_Backup_Memory(offset);
PRINTK_ANA_REG("Ana_Check_Backup_Memory ANA=0x%x, BACKUP=0x%x \n", val_1, val_2);
if(val_1 == val_2)
ret_value = 1;
else
ret_value = 0;
return (ret_value);
}
void Ana_Log_Print(void)
{
AudDrv_ANA_Clk_On();
printk("AFE_UL_DL_CON0 = 0x%x\n", Ana_Get_Reg(AFE_UL_DL_CON0));
printk("AFE_DL_SRC2_CON0_H = 0x%x\n", Ana_Get_Reg(AFE_DL_SRC2_CON0_H));
printk("AFE_DL_SRC2_CON0_L = 0x%x\n", Ana_Get_Reg(AFE_DL_SRC2_CON0_L));
printk("AFE_DL_SDM_CON0 = 0x%x\n", Ana_Get_Reg(AFE_DL_SDM_CON0));
printk("AFE_DL_SDM_CON1 = 0x%x\n", Ana_Get_Reg(AFE_DL_SDM_CON1));
printk("AFE_UL_SRC0_CON0_H = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC0_CON0_H));
printk("AFE_UL_SRC0_CON0_L = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC0_CON0_L));
printk("AFE_UL_SRC1_CON0_H = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC1_CON0_H));
printk("AFE_UL_SRC1_CON0_L = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC1_CON0_L));
printk("PMIC_AFE_TOP_CON0 = 0x%x\n", Ana_Get_Reg(PMIC_AFE_TOP_CON0));
printk("AFE_AUDIO_TOP_CON0 = 0x%x\n", Ana_Get_Reg(AFE_AUDIO_TOP_CON0));
printk("PMIC_AFE_TOP_CON0 = 0x%x\n", Ana_Get_Reg(PMIC_AFE_TOP_CON0));
printk("AFE_DL_SRC_MON0 = 0x%x\n", Ana_Get_Reg(AFE_DL_SRC_MON0));
printk("AFE_DL_SDM_TEST0 = 0x%x\n", Ana_Get_Reg(AFE_DL_SDM_TEST0));
printk("AFE_MON_DEBUG0 = 0x%x\n", Ana_Get_Reg(AFE_MON_DEBUG0));
printk("AFUNC_AUD_CON0 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON0));
printk("AFUNC_AUD_CON1 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON1));
printk("AFUNC_AUD_CON2 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON2));
printk("AFUNC_AUD_CON3 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON3));
printk("AFUNC_AUD_CON4 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON4));
printk("AFUNC_AUD_MON0 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_MON0));
printk("AFUNC_AUD_MON1 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_MON1));
printk("AUDRC_TUNE_MON0 = 0x%x\n", Ana_Get_Reg(AUDRC_TUNE_MON0));
printk("AFE_UP8X_FIFO_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_UP8X_FIFO_CFG0));
printk("AFE_UP8X_FIFO_LOG_MON0 = 0x%x\n", Ana_Get_Reg(AFE_UP8X_FIFO_LOG_MON0));
printk("AFE_UP8X_FIFO_LOG_MON1 = 0x%x\n", Ana_Get_Reg(AFE_UP8X_FIFO_LOG_MON1));
printk("AFE_DL_DC_COMP_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_DL_DC_COMP_CFG0));
printk("AFE_DL_DC_COMP_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_DL_DC_COMP_CFG1));
printk("AFE_DL_DC_COMP_CFG2 = 0x%x\n", Ana_Get_Reg(AFE_DL_DC_COMP_CFG2));
printk("AFE_PMIC_NEWIF_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG0));
printk("AFE_PMIC_NEWIF_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG1));
printk("AFE_PMIC_NEWIF_CFG2 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG2));
printk("AFE_PMIC_NEWIF_CFG3 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG3));
printk("AFE_SGEN_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_SGEN_CFG0));
printk("AFE_SGEN_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_SGEN_CFG1));
printk("AFE_VOW_TOP = 0x%x\n", Ana_Get_Reg(AFE_VOW_TOP));
printk("AFE_VOW_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG0));
printk("AFE_VOW_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG1));
printk("AFE_VOW_CFG2 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG2));
printk("AFE_VOW_CFG3 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG3));
printk("AFE_VOW_CFG4 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG4));
printk("AFE_VOW_CFG5 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG5));
printk("AFE_VOW_MON0 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON0));
printk("AFE_VOW_MON1 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON1));
printk("AFE_VOW_MON2 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON2));
printk("AFE_VOW_MON3 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON3));
printk("AFE_VOW_MON4 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON4));
printk("AFE_VOW_MON5 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON5));
printk("AFE_DCCLK_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_DCCLK_CFG0));
printk("AFE_DCCLK_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_DCCLK_CFG1));
printk("TOP_CON = 0x%x\n", Ana_Get_Reg(TOP_CON));
printk("TOP_STATUS = 0x%x\n", Ana_Get_Reg(TOP_STATUS));
printk("TOP_CKPDN_CON0 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON0));
printk("TOP_CKPDN_CON1 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON1));
printk("TOP_CKPDN_CON2 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON2));
printk("TOP_CKPDN_CON3 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON3));
printk("TOP_CKSEL_CON0 = 0x%x\n", Ana_Get_Reg(TOP_CKSEL_CON0));
printk("TOP_CKSEL_CON1 = 0x%x\n", Ana_Get_Reg(TOP_CKSEL_CON1));
printk("TOP_CKSEL_CON2 = 0x%x\n", Ana_Get_Reg(TOP_CKSEL_CON2));
printk("TOP_CKDIVSEL_CON = 0x%x\n", Ana_Get_Reg(TOP_CKDIVSEL_CON));
printk("TOP_CKHWEN_CON = 0x%x\n", Ana_Get_Reg(TOP_CKHWEN_CON));
printk("TOP_CKTST_CON0 = 0x%x\n", Ana_Get_Reg(TOP_CKTST_CON0));
printk("TOP_CKTST_CON1 = 0x%x\n", Ana_Get_Reg(TOP_CKTST_CON1));
printk("TOP_CKTST_CON2 = 0x%x\n", Ana_Get_Reg(TOP_CKTST_CON2));
printk("TOP_CLKSQ = 0x%x\n", Ana_Get_Reg(TOP_CLKSQ));
printk("TOP_RST_CON0 = 0x%x\n", Ana_Get_Reg(TOP_RST_CON0));
printk("ZCD_CON0 = 0x%x\n", Ana_Get_Reg(ZCD_CON0));
printk("ZCD_CON1 = 0x%x\n", Ana_Get_Reg(ZCD_CON1));
printk("ZCD_CON2 = 0x%x\n", Ana_Get_Reg(ZCD_CON2));
printk("ZCD_CON3 = 0x%x\n", Ana_Get_Reg(ZCD_CON3));
printk("ZCD_CON4 = 0x%x\n", Ana_Get_Reg(ZCD_CON4));
printk("ZCD_CON5 = 0x%x\n", Ana_Get_Reg(ZCD_CON5));
printk("LDO_CON1 = 0x%x\n", Ana_Get_Reg(LDO_CON1));
printk("LDO_CON2 = 0x%x\n", Ana_Get_Reg(LDO_CON2));
printk("LDO_VCON1 = 0x%x\n", Ana_Get_Reg(LDO_VCON1));
printk("SPK_CON0 = 0x%x\n", Ana_Get_Reg(SPK_CON0));
printk("SPK_CON1 = 0x%x\n", Ana_Get_Reg(SPK_CON1));
printk("SPK_CON2 = 0x%x\n", Ana_Get_Reg(SPK_CON2));
printk("SPK_CON3 = 0x%x\n", Ana_Get_Reg(SPK_CON3));
printk("SPK_CON4 = 0x%x\n", Ana_Get_Reg(SPK_CON4));
printk("SPK_CON5 = 0x%x\n", Ana_Get_Reg(SPK_CON5));
printk("SPK_CON6 = 0x%x\n", Ana_Get_Reg(SPK_CON6));
printk("SPK_CON7 = 0x%x\n", Ana_Get_Reg(SPK_CON7));
printk("SPK_CON8 = 0x%x\n", Ana_Get_Reg(SPK_CON8));
printk("SPK_CON9 = 0x%x\n", Ana_Get_Reg(SPK_CON9));
printk("SPK_CON10 = 0x%x\n", Ana_Get_Reg(SPK_CON10));
printk("SPK_CON11 = 0x%x\n", Ana_Get_Reg(SPK_CON11));
printk("SPK_CON12 = 0x%x\n", Ana_Get_Reg(SPK_CON12));
printk("SPK_CON13 = 0x%x\n", Ana_Get_Reg(SPK_CON13));
printk("SPK_CON14 = 0x%x\n", Ana_Get_Reg(SPK_CON14));
printk("SPK_CON15 = 0x%x\n", Ana_Get_Reg(SPK_CON15));
printk("SPK_CON16 = 0x%x\n", Ana_Get_Reg(SPK_CON16));
printk("SPK_ANA_CON0 = 0x%x\n", Ana_Get_Reg(SPK_ANA_CON0));
printk("SPK_ANA_CON1 = 0x%x\n", Ana_Get_Reg(SPK_ANA_CON1));
printk("SPK_ANA_CON3 = 0x%x\n", Ana_Get_Reg(SPK_ANA_CON3));
printk("AUDDEC_ANA_CON0 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON0));
printk("AUDDEC_ANA_CON1 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON1));
printk("AUDDEC_ANA_CON2 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON2));
printk("AUDDEC_ANA_CON3 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON3));
printk("AUDDEC_ANA_CON4 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON4));
printk("AUDDEC_ANA_CON5 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON5));
printk("AUDDEC_ANA_CON6 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON6));
printk("AUDDEC_ANA_CON7 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON7));
printk("AUDDEC_ANA_CON8 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON8));
printk("AUDENC_ANA_CON0 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON0));
printk("AUDENC_ANA_CON1 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON1));
printk("AUDENC_ANA_CON2 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON2));
printk("AUDENC_ANA_CON3 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON3));
printk("AUDENC_ANA_CON4 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON4));
printk("AUDENC_ANA_CON5 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON5));
printk("AUDENC_ANA_CON6 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON6));
printk("AUDENC_ANA_CON7 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON7));
printk("AUDENC_ANA_CON8 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON8));
printk("AUDENC_ANA_CON9 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON9));
printk("AUDENC_ANA_CON11 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON11));
printk("AUDENC_ANA_CON12 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON12));
printk("AUDENC_ANA_CON13 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON13));
printk("AUDENC_ANA_CON14 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON14));
printk("AUDENC_ANA_CON15 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON15));
printk("AUDNCP_CLKDIV_CON0 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON0));
printk("AUDNCP_CLKDIV_CON1 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON1));
printk("AUDNCP_CLKDIV_CON2 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON2));
printk("AUDNCP_CLKDIV_CON3 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON3));
printk("AUDNCP_CLKDIV_CON4 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON4));
printk("TOP_CKPDN_CON0 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON0));
printk("GPIO_MODE3 = 0x%x\n", Ana_Get_Reg(GPIO_MODE3));
printk("AFE_VOW_POSDIV_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_VOW_POSDIV_CFG0));
AudDrv_ANA_Clk_Off();
printk("-Ana_Log_Print \n");
}
void Ana_Log_Print(void)
{
AudDrv_ANA_Clk_On();
pr_warn("ABB_AFE_CON0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON0));
pr_warn("ABB_AFE_CON1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON1));
pr_warn("ABB_AFE_CON2 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON2));
pr_warn("ABB_AFE_CON3 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON3));
pr_warn("ABB_AFE_CON4 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON4));
pr_warn("ABB_AFE_CON5 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON5));
pr_warn("ABB_AFE_CON6 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON6));
pr_warn("ABB_AFE_CON7 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON7));
pr_warn("ABB_AFE_CON8 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON8));
pr_warn("ABB_AFE_CON9 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON9));
pr_warn("ABB_AFE_CON10 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON10));
pr_warn("ABB_AFE_CON11 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON11));
pr_warn("ABB_AFE_STA0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_STA0));
pr_warn("ABB_AFE_STA1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_STA1));
pr_warn("ABB_AFE_STA2 = 0x%x\n", Ana_Get_Reg(ABB_AFE_STA2));
pr_warn("ABB_AFE_UP8X_FIFO_CFG0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_UP8X_FIFO_CFG0));
pr_warn("ABB_AFE_UP8X_FIFO_LOG_MON0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_UP8X_FIFO_LOG_MON0));
pr_warn("ABB_AFE_UP8X_FIFO_LOG_MON1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_UP8X_FIFO_LOG_MON1));
pr_warn("ABB_AFE_PMIC_NEWIF_CFG0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_PMIC_NEWIF_CFG0));
pr_warn("ABB_AFE_PMIC_NEWIF_CFG1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_PMIC_NEWIF_CFG1));
pr_warn("ABB_AFE_PMIC_NEWIF_CFG2 = 0x%x\n", Ana_Get_Reg(ABB_AFE_PMIC_NEWIF_CFG2));
pr_warn("ABB_AFE_PMIC_NEWIF_CFG3 = 0x%x\n", Ana_Get_Reg(ABB_AFE_PMIC_NEWIF_CFG3));
pr_warn("ABB_AFE_TOP_CON0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_TOP_CON0));
pr_warn("ABB_AFE_MON_DEBUG0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_MON_DEBUG0));
pr_warn("SPK_CON0 = 0x%x\n", Ana_Get_Reg(SPK_CON0));
pr_warn("SPK_CON1 = 0x%x\n", Ana_Get_Reg(SPK_CON1));
pr_warn("SPK_CON2 = 0x%x\n", Ana_Get_Reg(SPK_CON2));
pr_warn("SPK_CON6 = 0x%x\n", Ana_Get_Reg(SPK_CON6));
pr_warn("SPK_CON7 = 0x%x\n", Ana_Get_Reg(SPK_CON7));
pr_warn("SPK_CON8 = 0x%x\n", Ana_Get_Reg(SPK_CON8));
pr_warn("SPK_CON9 = 0x%x\n", Ana_Get_Reg(SPK_CON9));
pr_warn("SPK_CON10 = 0x%x\n", Ana_Get_Reg(SPK_CON10));
pr_warn("SPK_CON11 = 0x%x\n", Ana_Get_Reg(SPK_CON11));
pr_warn("SPK_CON12 = 0x%x\n", Ana_Get_Reg(SPK_CON12));
pr_warn("CID = 0x%x\n", Ana_Get_Reg(CID));
pr_warn("TOP_CKPDN0 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN0));
pr_warn("TOP_CKPDN0_SET = 0x%x\n", Ana_Get_Reg(TOP_CKPDN0_SET));
pr_warn("TOP_CKPDN0_CLR = 0x%x\n", Ana_Get_Reg(TOP_CKPDN0_CLR));
pr_warn("TOP_CKPDN1 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN1));
pr_warn("TOP_CKPDN1_SET = 0x%x\n", Ana_Get_Reg(TOP_CKPDN1_SET));
pr_warn("TOP_CKPDN1_CLR = 0x%x\n", Ana_Get_Reg(TOP_CKPDN1_CLR));
pr_warn("TOP_CKPDN2 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN2));
pr_warn("TOP_CKPDN2_SET = 0x%x\n", Ana_Get_Reg(TOP_CKPDN2_SET));
pr_warn("TOP_CKPDN2_CLR = 0x%x\n", Ana_Get_Reg(TOP_CKPDN2_CLR));
pr_warn("TOP_CKCON1 = 0x%x\n", Ana_Get_Reg(TOP_CKCON1));
pr_warn("AUDTOP_CON0 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON0));
pr_warn("AUDTOP_CON1 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON1));
pr_warn("AUDTOP_CON2 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON2));
pr_warn("AUDTOP_CON3 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON3));
pr_warn("AUDTOP_CON4 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON4));
pr_warn("AUDTOP_CON5 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON5));
pr_warn("AUDTOP_CON6 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON6));
pr_warn("AUDTOP_CON7 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON7));
pr_warn("AUDTOP_CON8 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON8));
pr_warn("AUDTOP_CON9 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON9));
AudDrv_ANA_Clk_Off();
pr_warn("-Ana_Log_Print\n");
}
static int mtk_capture_alsa_start(struct snd_pcm_substream *substream)
{
printk("mtk_capture_alsa_start \n");
SetMemifSubStream(Soc_Aud_Digital_Block_MEM_VUL, substream);
StartAudioCaptureHardware(substream);
#ifdef DENALI_FPGA_EARLYPORTING //ccc early porting, copy from TurnOnDacPower() and ADC_LOOP_DAC_Func()
// Afe_Set_Reg(AFE_SGEN_CON0, 0x24862862, 0xffffffff);
// Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0002, 0x0002); //UL from sinetable
// Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0001, 0x0001); //DL from sinetable
// Ana_Set_Reg(AFE_SGEN_CFG0 , 0x0080 , 0xffff);
// Ana_Set_Reg(AFE_SGEN_CFG1 , 0x0101 , 0xffff);
Ana_Get_Reg(AFE_AUDIO_TOP_CON0); //power on clock
Ana_Get_Reg(AFUNC_AUD_CON2);
Ana_Get_Reg(AFUNC_AUD_CON0); //sdm audio fifo clock power on
Ana_Get_Reg(AFUNC_AUD_CON2); //sdm power on
Ana_Get_Reg(AFUNC_AUD_CON2); //sdm fifo enable
Ana_Get_Reg(AFE_DL_SDM_CON1); //set attenuation gain
Ana_Get_Reg(AFE_UL_DL_CON0); //[0] afe enable
Ana_Get_Reg(AFE_PMIC_NEWIF_CFG0); //8k sample rate
Ana_Get_Reg(AFE_DL_SRC2_CON0_H);//8k sample rate
Ana_Get_Reg(AFE_DL_SRC2_CON0_L); //turn off mute function and turn on dl
Ana_Get_Reg(PMIC_AFE_TOP_CON0); //set DL in normal path, not from sine gen table
Ana_Get_Reg(AFE_SGEN_CFG0); //set DL in normal path, not from sine gen table
Ana_Get_Reg(AFE_SGEN_CFG1); //set DL in normal path, not from sine gen table
Ana_Get_Reg(TOP_CLKSQ); //Enable CLKSQ 26MHz
Ana_Get_Reg(TOP_CLKSQ_SET); //Turn on 26MHz source clock
Ana_Get_Reg(AFE_AUDIO_TOP_CON0); //power on clock
Ana_Get_Reg(FPGA_CFG1); // must set in FPGA platform for PMIC digital loopback
#endif
return 0;
}
static ssize_t mt_soc_debug_write(struct file *f, const char __user *buf,
size_t count, loff_t *offset)
{
int ret = 0;
char InputString[256];
char *token1 = NULL ;
char *token2 = NULL ;
char *token3 = NULL;
char *token4 = NULL;
char *token5 = NULL;
char *temp = NULL;
long unsigned int regaddr = 0;
long unsigned int regvalue = 0;
char delim[] = " ,";
memset((void *)InputString, 0, 256);
if (copy_from_user((InputString), buf, count))
{
printk("copy_from_user mt_soc_debug_write count = %zu temp = %s\n", count, InputString);
}
temp = kstrdup(InputString, GFP_KERNEL);
printk("copy_from_user mt_soc_debug_write count = %zu temp = %s pointer = %p\n", count, InputString, InputString);
token1 = strsep(&temp, delim);
printk("token1 \n");
printk("token1 = %s\n", token1);
token2 = strsep(&temp, delim);
printk("token2 = %s\n", token2);
token3 = strsep(&temp, delim);
printk("token3 = %s\n", token3);
token4 = strsep(&temp, delim);
printk("token4 = %s\n", token4);
token5 = strsep(&temp, delim);
printk("token5 = %s\n", token5);
if (strcmp(token1, ParSetkeyAfe) == 0)
{
printk("strcmp (token1,ParSetkeyAfe) \n");
ret = strict_strtoul(token3, 16, ®addr);
ret = strict_strtoul(token5, 16, ®value);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyAfe, regaddr, regvalue);
Afe_Set_Reg(regaddr, regvalue, 0xffffffff);
regvalue = Afe_Get_Reg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyAfe, regaddr, regvalue);
}
if (strcmp(token1, ParSetkeyAna) == 0)
{
printk("strcmp (token1,ParSetkeyAna)\n");
ret = strict_strtoul(token3, 16, ®addr);
ret = strict_strtoul(token5, 16, ®value);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyAna, regaddr, regvalue);
//clk_buf_ctrl(CLK_BUF_AUDIO, true); //k2 need?
AudDrv_Clk_On();
audckbufEnable(true);
Ana_Set_Reg(regaddr, regvalue, 0xffffffff);
regvalue = Ana_Get_Reg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyAna, regaddr, regvalue);
}
if (strcmp(token1, ParSetkeyCfg) == 0)
{
printk("strcmp (token1,ParSetkeyCfg)\n");
ret = strict_strtoul(token3, 16, ®addr);
ret = strict_strtoul(token5, 16, ®value);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyCfg, regaddr, regvalue);
SetClkCfg(regaddr, regvalue, 0xffffffff);
regvalue = GetClkCfg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyCfg, regaddr, regvalue);
}
if (strcmp(token1, PareGetkeyAfe) == 0)
{
printk("strcmp (token1,PareGetkeyAfe)\n");
ret = strict_strtoul(token3, 16, ®addr);
regvalue = Afe_Get_Reg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", PareGetkeyAfe, regaddr, regvalue);
}
if (strcmp(token1, PareGetkeyAna) == 0)
{
printk("strcmp (token1,PareGetkeyAna)\n");
ret = strict_strtoul(token3, 16, ®addr);
regvalue = Ana_Get_Reg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", PareGetkeyAna, regaddr, regvalue);
}
return count;
}
static ssize_t mt_soc_ana_debug_read(struct file *file, char __user *buf,
size_t count, loff_t *pos)
{
const int size = 4096;
char buffer[size];
int n = 0;
printk("mt_soc_ana_debug_read count = %zu\n", count);
AudDrv_Clk_On();
audckbufEnable(true);
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON0));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON1));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON2 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON2));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON3 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON3));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON4 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON4));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON5 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON5));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON6 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON6));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON7 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON7));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON8 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON8));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON9 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON9));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON10 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON10));
n += scnprintf(buffer + n, size - n, "ABB_AFE_CON11 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON11));
n += scnprintf(buffer + n, size - n, "ABB_AFE_STA0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_STA0));
n += scnprintf(buffer + n, size - n, "ABB_AFE_STA1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_STA1));
n += scnprintf(buffer + n, size - n, "ABB_AFE_STA2 = 0x%x\n", Ana_Get_Reg(ABB_AFE_STA2));
n += scnprintf(buffer + n, size - n, "AFE_UP8X_FIFO_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_UP8X_FIFO_CFG0));
n += scnprintf(buffer + n, size - n, "AFE_UP8X_FIFO_LOG_MON0 = 0x%x\n", Ana_Get_Reg(AFE_UP8X_FIFO_LOG_MON0));
n += scnprintf(buffer + n, size - n, "AFE_UP8X_FIFO_LOG_MON1 = 0x%x\n", Ana_Get_Reg(AFE_UP8X_FIFO_LOG_MON1));
n += scnprintf(buffer + n, size - n, "AFE_PMIC_NEWIF_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG0));
n += scnprintf(buffer + n, size - n, "AFE_PMIC_NEWIF_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG1));
n += scnprintf(buffer + n, size - n, "AFE_PMIC_NEWIF_CFG2 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG2));
n += scnprintf(buffer + n, size - n, "AFE_PMIC_NEWIF_CFG3 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG3));
n += scnprintf(buffer + n, size - n, "ABB_AFE_TOP_CON0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_TOP_CON0));
n += scnprintf(buffer + n, size - n, "ABB_MON_DEBUG0 = 0x%x\n", Ana_Get_Reg(ABB_MON_DEBUG0));
n += scnprintf(buffer + n, size - n, "TOP_CKPDN0 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN0));
n += scnprintf(buffer + n, size - n, "TOP_CKPDN1 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN1));
n += scnprintf(buffer + n, size - n, "TOP_CKPDN2 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN2));
n += scnprintf(buffer + n, size - n, "TOP_CKCON1 = 0x%x\n", Ana_Get_Reg(TOP_CKCON1));
n += scnprintf(buffer + n, size - n, "SPK_CON0 = 0x%x\n", Ana_Get_Reg(SPK_CON0));
n += scnprintf(buffer + n, size - n, "SPK_CON1 = 0x%x\n", Ana_Get_Reg(SPK_CON1));
n += scnprintf(buffer + n, size - n, "SPK_CON2 = 0x%x\n", Ana_Get_Reg(SPK_CON2));
n += scnprintf(buffer + n, size - n, "SPK_CON6 = 0x%x\n", Ana_Get_Reg(SPK_CON6));
n += scnprintf(buffer + n, size - n, "SPK_CON7 = 0x%x\n", Ana_Get_Reg(SPK_CON7));
n += scnprintf(buffer + n, size - n, "SPK_CON8 = 0x%x\n", Ana_Get_Reg(SPK_CON8));
n += scnprintf(buffer + n, size - n, "SPK_CON9 = 0x%x\n", Ana_Get_Reg(SPK_CON9));
n += scnprintf(buffer + n, size - n, "SPK_CON10 = 0x%x\n", Ana_Get_Reg(SPK_CON10));
n += scnprintf(buffer + n, size - n, "SPK_CON11 = 0x%x\n", Ana_Get_Reg(SPK_CON11));
n += scnprintf(buffer + n, size - n, "SPK_CON12 = 0x%x\n", Ana_Get_Reg(SPK_CON12));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON0 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON0));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON1 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON1));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON2 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON2));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON3 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON3));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON4 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON4));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON5 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON5));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON6 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON6));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON7 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON7));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON8 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON8));
n += scnprintf(buffer + n, size - n, "AUDTOP_CON9 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON9));
printk("mt_soc_ana_debug_read len = %d\n", n);
audckbufEnable(false);
AudDrv_Clk_Off();
return simple_read_from_buffer(buf, count, pos, buffer, n);
}
