static void enable_videopll(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; s32 timeout = 100000; setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); /* set video pll to 910MHz (24MHz * (37+11/12)) * video pll post div to 910/4 = 227.5MHz */ clrsetbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_DIV_SELECT | BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0)); writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); while (timeout--) if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) break; if (timeout < 0) printf("Warning: video pll lock timeout!\n"); clrsetbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_BYPASS, BM_ANADIG_PLL_VIDEO_ENABLE); }
static void setup_display(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; s32 timeout = 100000; enable_ipu_clock(); imx_setup_hdmi(); /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ reg = readl(&ccm->analog_pll_video); reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; writel(reg, &ccm->analog_pll_video); reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); writel(reg, &ccm->analog_pll_video); writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; writel(reg, &ccm->analog_pll_video); while (timeout--) if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) break; if (timeout < 0) printf("Warning: video pll lock timeout!\n"); reg = readl(&ccm->analog_pll_video); reg |= BM_ANADIG_PLL_VIDEO_ENABLE; reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; writel(reg, &ccm->analog_pll_video); /* gate ipu1_di0_clk */ reg = readl(&ccm->CCGR3); reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK; writel(reg, &ccm->CCGR3); /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ reg = readl(&ccm->chsccdr); reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &ccm->chsccdr); /* enable ipu1_di0_clk */ reg = readl(&ccm->CCGR3); reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; writel(reg, &ccm->CCGR3); }
static void enable_spi_display(struct display_info_t const *dev) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; s32 timeout = 100000; #if defined(CONFIG_VIDEO_BMP_LOGO) rotate_logo(3); /* portrait display in landscape mode */ #endif /* * set ldb clock to 28341000 Hz calculated through the formula: * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) * * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH) * see: * https://community.freescale.com/thread/308170 */ ipu_set_ldb_clock(28341000); reg = readl(&ccm->cs2cdr); /* select pll 5 clock */ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); writel(reg, &ccm->cs2cdr); /* set PLL5 to 197994996Hz */ reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); writel(reg, &ccm->analog_pll_video); writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), &ccm->analog_pll_video_num); writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), &ccm->analog_pll_video_denom); reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; writel(reg, &ccm->analog_pll_video); while (timeout--) if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) break; if (timeout < 0) printf("Warning: video pll lock timeout!\n"); reg = readl(&ccm->analog_pll_video); reg |= BM_ANADIG_PLL_VIDEO_ENABLE; reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; writel(reg, &ccm->analog_pll_video); /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ reg = readl(&ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); writel(reg, &ccm->cs2cdr); reg = readl(&ccm->cscmr2); reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; writel(reg, &ccm->cscmr2); reg = readl(&ccm->chsccdr); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); writel(reg, &ccm->chsccdr); reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; writel(reg, &iomux->gpr[2]); reg = readl(&iomux->gpr[3]); reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); writel(reg, &iomux->gpr[3]); imx_iomux_v3_setup_multiple_pads( display_pads, ARRAY_SIZE(display_pads)); return; }
static void enable_lvds(struct display_info_t const *dev) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; s32 timeout = 100000; /* set PLL5 clock */ reg = readl(&ccm->analog_pll_video); reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; writel(reg, &ccm->analog_pll_video); /* set PLL5 to 232720000Hz */ reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26); reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); writel(reg, &ccm->analog_pll_video); writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238), &ccm->analog_pll_video_num); writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240), &ccm->analog_pll_video_denom); reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; writel(reg, &ccm->analog_pll_video); while (timeout--) if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) break; if (timeout < 0) printf("Warning: video pll lock timeout!\n"); reg = readl(&ccm->analog_pll_video); reg |= BM_ANADIG_PLL_VIDEO_ENABLE; reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; writel(reg, &ccm->analog_pll_video); /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ reg = readl(&ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); writel(reg, &ccm->cs2cdr); reg = readl(&ccm->cscmr2); reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; writel(reg, &ccm->cscmr2); reg = readl(&ccm->chsccdr); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &ccm->chsccdr); reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; writel(reg, &iomux->gpr[2]); reg = readl(&iomux->gpr[3]); reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); writel(reg, &iomux->gpr[3]); return; }