void loop() { while (true) { STOP(); STOP(); STOP(); STOP(); STOP(); STOP(); STOP(); STOP(); STOP(); IDLE(); BIT0(); BIT0(); BIT1(); BIT1(); BIT0(); BIT1(); BIT1(); BIT0(); STOP(); } }
int main() { int ch; if (map_peripheral(&gpio) == -1) { printf("Failed to map the physical GPIO registers into the virtual memory space.\n"); return -1; } // Define pin as output INP_GPIO(PIN); OUT_GPIO(PIN); BIT1(); while((ch = getchar()) != EOF) { short bit; usleep(4000); BIT0(); // start usleep(BITLEN); for (bit = 1; bit != 0x100; bit <<= 1) { if (bit & ch) BIT1(); else BIT0(); usleep(BITLEN); } BIT1(); // stop usleep(BITLEN); } return 0; }
/* * Make the table local in * linux-2.6.27.y/drivers/mtd/nand/nand_ecc.c */ void mkECCtbl(void) { unsigned char i; unsigned cp0, cp1, cp2, cp3, cp4, cp5; unsigned rp; cp0 = 0, cp1 = 0, cp2 = 0, cp3 = 0, cp4 = 0, cp5 = 0; rp = 0; /* * cp0 = bit6 ^ bit4 ^ bit2 ^ bit0; * cp1 = bit7 ^ bit5 ^ bit3 ^ bit1; * cp2 = bit5 ^ bit4 ^ bit1 ^ bit0; * cp3 = bit7 ^ bit6 ^ bit3 ^ bit2; * cp4 = bit3 ^ bit2 ^ bit1 ^ bit0; * cp5 = bit7 ^ bit6 ^ bit5 ^ bit4; * * rp = xor all bits; */ for (i = 0; i < 0xff; i++) { unsigned char xdata = 0; cp0 = BIT0(i) ^ BIT2(i) ^ BIT4(i) ^ BIT6(i); if (cp0) xdata |= 0x1; cp1 = BIT1(i) ^ BIT3(i) ^ BIT5(i) ^ BIT7(i); if (cp1) xdata |= 0x2; cp2 = BIT0(i) ^ BIT1(i) ^ BIT4(i) ^ BIT5(i); if (cp2) xdata |= 0x4; cp3 = BIT2(i) ^ BIT3(i) ^ BIT6(i) ^ BIT7(i); if (cp3) xdata |= 0x8; cp4 = BIT0(i) ^ BIT1(i) ^ BIT2(i) ^ BIT3(i); if (cp4) xdata |= 0x10; cp5 = BIT4(i) ^ BIT5(i) ^ BIT6(i) ^ BIT7(i); if (cp5) xdata |= 0x20; rp = BIT0(i) ^ BIT1(i) ^ BIT2(i) ^ BIT3(i) ^ BIT4(i) ^ BIT5(i) ^ BIT6(i) ^ BIT7(i); if (rp) xdata |= 0x40; ecc_tbl[i] = xdata; } }
static void calculate_ecc(const uint8_t *buf, uint8_t *ecc) { uint8_t p8, byte; int i; memset(ecc, 0, 3); for (i = 0; i < 256; i++) { byte = buf[i]; ecc[0] ^= (BIT0(byte) ^ BIT2(byte) ^ BIT4(byte) ^ BIT6(byte)) << 2; ecc[0] ^= (BIT1(byte) ^ BIT3(byte) ^ BIT5(byte) ^ BIT7(byte)) << 3; ecc[0] ^= (BIT0(byte) ^ BIT1(byte) ^ BIT4(byte) ^ BIT5(byte)) << 4; ecc[0] ^= (BIT2(byte) ^ BIT3(byte) ^ BIT6(byte) ^ BIT7(byte)) << 5; ecc[0] ^= (BIT0(byte) ^ BIT1(byte) ^ BIT2(byte) ^ BIT3(byte)) << 6; ecc[0] ^= (BIT4(byte) ^ BIT5(byte) ^ BIT6(byte) ^ BIT7(byte)) << 7; p8 = BIT0(byte) ^ BIT1(byte) ^ BIT2(byte) ^ BIT3(byte) ^ BIT4(byte) ^ BIT5(byte) ^ BIT6(byte) ^ BIT7(byte); if (p8) { ecc[2] ^= (0x1 << BIT0(i)); ecc[2] ^= (0x4 << BIT1(i)); ecc[2] ^= (0x10 << BIT2(i)); ecc[2] ^= (0x40 << BIT3(i)); ecc[1] ^= (0x1 << BIT4(i)); ecc[1] ^= (0x4 << BIT5(i)); ecc[1] ^= (0x10 << BIT6(i)); ecc[1] ^= (0x40 << BIT7(i)); } } ecc[0] = ~ecc[0]; ecc[1] = ~ecc[1]; ecc[2] = ~ecc[2]; ecc[0] |= 3; }
static int correct_ecc(uint8_t *buf, uint8_t *calc_ecc, uint8_t *read_ecc) { uint8_t ecc0, ecc1, ecc2, onesnum, bit, byte; uint16_t addr = 0; ecc0 = calc_ecc[0] ^ read_ecc[0]; ecc1 = calc_ecc[1] ^ read_ecc[1]; ecc2 = calc_ecc[2] ^ read_ecc[2]; if (!ecc0 && !ecc1 && !ecc2) return (ECC_OK); addr = BIT3(ecc0) | (BIT5(ecc0) << 1) | (BIT7(ecc0) << 2); addr |= (BIT1(ecc2) << 3) | (BIT3(ecc2) << 4) | (BIT5(ecc2) << 5) | (BIT7(ecc2) << 6); addr |= (BIT1(ecc1) << 7) | (BIT3(ecc1) << 8) | (BIT5(ecc1) << 9) | (BIT7(ecc1) << 10); onesnum = 0; while (ecc0 || ecc1 || ecc2) { if (ecc0 & 1) onesnum++; if (ecc1 & 1) onesnum++; if (ecc2 & 1) onesnum++; ecc0 >>= 1; ecc1 >>= 1; ecc2 >>= 1; } if (onesnum == 11) { /* Correctable error */ bit = addr & 7; byte = addr >> 3; buf[byte] ^= (1 << bit); return (ECC_CORRECTABLE); } else if (onesnum == 1) {
/* For clocks with MND dividers. */ void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf) { uint32_t ns_reg_val, ctl_reg_val; /* Assert MND reset. */ ns_reg_val = readl_relaxed(clk->ns_reg); ns_reg_val |= BIT1(7); writel_relaxed(ns_reg_val, clk->ns_reg); /* Program M and D values. */ writel_relaxed(nf->md_val, clk->md_reg); /* If the clock has a separate CC register, program it. */ if (clk->ns_reg != clk->b.ctl_reg) { ctl_reg_val = readl_relaxed(clk->b.ctl_reg); ctl_reg_val &= ~(clk->ctl_mask); ctl_reg_val |= nf->ctl_val; writel_relaxed(ctl_reg_val, clk->b.ctl_reg); } /* Deassert MND reset. */ ns_reg_val &= ~BIT1(7); writel_relaxed(ns_reg_val, clk->ns_reg); }
/* * Clock enable/disable functions */ static int branch_clk_is_halted(const struct branch *clk) { int invert = (clk->halt_check == ENABLE); int status_bit = readl_relaxed(clk->halt_reg) & BIT1(clk->halt_bit); return invert ? !status_bit : status_bit; }