static void LED_Update(void)
{
BITBAND_REG(GPIOD->ODR, 2) = 1;
GPIOC->ODR = ((led_status<<8)&0x0000FF00)|(GPIOC->ODR&(~0x0000FF00));
BITBAND_REG(GPIOD->ODR, 2) = 0;
}
void spi_stop(const spi_bus_t spi_num)
{
/* Enable clock gate for the correct SPI hardware module */
switch(spi_num) {
case SPI_0:
BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0;
break;
case SPI_1:
BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 0;
break;
case SPI_2:
BITBAND_REG(SIM->SCGC3, SIM_SCGC3_SPI2_SHIFT) = 0;
break;
}
}
void SetupPorts(void) {
SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK);
//Servo Register
PORTA_PCR8 = PORT_PCR_MUX(3) | PORT_PCR_DSE_MASK; // CH0 // A34 - tested
//Motor Registers
PORTD_PCR4 = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK; // CH4 B40 -tested
PORTC_PCR4 = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK; // CH3 //A37 - tested
PORTD_PCR5 = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;//PTD5 // B39 -tested -- ch5
PORTD_PCR6 = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;//PTD6 // B34 -tested -- ch6
//GPIO Registers
PORTA_PCR7 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; // // B69 -- GPIO -- high
PORTA_PCR6 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; // // A64 -- GPIO -- d1a
PORTA_PCR12 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; // // A25 -- GPIO -- d1b
//Set GPIO Direction
BITBAND_REG(GPIOA_PDDR,6) = 1;
BITBAND_REG(GPIOA_PDDR,7) = 1;
BITBAND_REG(GPIOA_PDDR,12) = 1;
//Set GPIO Value
BITBAND_REG(GPIOA_PSOR, 7) = 1;
// LEDs
//Important! Each IO pin has a dedicated 32-bit Register to set it up (Selection GPIO vs peripheral, IRQ, Etc.)
//Setup port C7 as GPIO and enable High Drive Strength
PORTC_PCR7 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; //Enable GPIO on on the pin
PORTC_PCR8 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; //Enable GPIO on on the pin
PORTC_PCR9 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; //Enable GPIO on on the pin
PORTB_PCR11 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; //Enable GPIO on on the pin
//Make Sure the GPIO is setup to be an output
GPIOC_PDDR |= (LED_E1_LOC | LED_E2_LOC | LED_E3_LOC);
GPIOB_PDDR |= LED_E4_LOC;
}
void
spi_hw_init_master(const spi_bus_t spi_num) {
/* Clear lock variable */
spi_lock[spi_num] = 0;
/* Block access to the bus */
spi_acquire_bus(spi_num);
/* enable clock gate */
spi_start(spi_num);
/* Clear MDIS to enable the module. */
BITBAND_REG(SPI[spi_num]->MCR, SPI_MCR_MDIS_SHIFT) = 0;
/* Enable master mode, select chip select signal polarity */
/* XXX: Hard-coded chip select active low */
/* Disable FIFOs, this can be improved in the future */
SPI[spi_num]->MCR = SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS(0x1F) | SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
/* Enable interrupts for TCF flag */
BITBAND_REG(SPI[spi_num]->RSER, SPI_RSER_TCF_RE_SHIFT) = 1;
switch(spi_num) {
case SPI_0:
NVIC_EnableIRQ(SPI0_IRQn);
break;
case SPI_1:
NVIC_EnableIRQ(SPI1_IRQn);
break;
case SPI_2:
NVIC_EnableIRQ(SPI2_IRQn);
break;
}
/* disable clock gate */
spi_stop(spi_num);
/* Allow access to the bus */
spi_release_bus(spi_num);
}
void USART2_IRQHandler(void)
{
if (BITBAND_REG(USART2->SR, 5))
{
usart_buf[buf_index] = USART2->DR;
if (usart_buf[buf_index] == '\n')
{
usart_buf[buf_index+1] = '\0';
USART2_GetPacket(usart_buf);
buf_index = 0;
}
else
{
buf_index++;
}
}
}
void _isr_spi1(void) {
/* Clear status flag by writing a 1 to it */
BITBAND_REG(SPI1->SR, SPI_SR_TCF_SHIFT) = 1;
spi_waiting_flag[1] = 0;
}
