int32_t ADC_GetValues(adc_channel id, bool scale, uint8_t num, int32_t *p_buf)
{
int32_t count;
uint8_t i;
/* clear int */
ANA_REG_OR(ADC_INT_CLR, ADC_IRQ_CLR_BIT);
/* choose channel */
ADC_SetCs(id);
/* set ADC scale */
ADC_SetScale(scale);
/* set read numbers run ADC soft channel */
if (num < 1) {
return -1;
}
ANA_REG_MSK_OR(ADC_CTRL, BIT_SW_CH_RUN_NUM(num), SW_CH_NUM_MSK);
ANA_REG_OR(ADC_CTRL, SW_CH_ON_BIT);
/* wait adc complete */
count = 1000;
while(!(ANA_REG_GET(ADC_INT_SRC)&ADC_IRQ_RAW_BIT) && count--) {
for (i = 0; i < 0xFF; i++);
}
if (count <= 0) {
pr_warning("WARNING: ADC_GetValue timeout....\n");
return -1;
}
for (i = 0; i < num; i++) {
p_buf[i] = ANA_REG_GET(ADC_DAT) & ADC_DATA_MSK;
}
ANA_REG_AND(ADC_CTRL, ~SW_CH_ON_BIT); // turn off adc soft channel
return 0;
}
int sci_adc_get_values(struct adc_sample_data *adc)
{
unsigned long flags, hw_flags;
int cnt = 12;
unsigned addr = 0;
unsigned val = 0;
int ret = 0;
int num = 0;
int sample_bits_msk = 0;
int *pbuf = 0;
if (!adc || adc->channel_id > ADC_MAX)
return -EINVAL;
pbuf = adc->pbuf;
if (!pbuf)
return -EINVAL;
num = adc->sample_num;
if (num > ADC_MAX_SAMPLE_NUM)
return -EINVAL;
sci_adc_lock();
sci_adc_config(adc); //configs adc sample.
addr = io_base + ADC_CTL;
val = adc_read(addr);
val &= ~(BIT_ADC_EN | BIT_SW_CH_ON | BIT_ADC_BIT_MODE_MASK);
adc_write(val, addr);
adc_clear_irq();
val = BIT_SW_CH_RUN_NUM(num);
val |= BIT_ADC_EN;
val |= BIT_ADC_BIT_MODE(adc->sample_bits);
val |= BIT_SW_CH_ON;
adc_write(val, addr);
while ((!adc_raw_irqstatus()) && cnt--) {
udelay(50);
}
if (!cnt) {
ret = -1;
WARN_ON(1);
goto Exit;
}
if (adc->sample_bits)
sample_bits_msk = ((1 << 12) - 1); //12
else
sample_bits_msk = ((1 << 10) - 1); //10
while (num--)
*pbuf++ = adc_get_data(sample_bits_msk);
Exit:
val = adc_read(addr);
val &= ~BIT_ADC_EN;
adc_write(val, addr);
sci_adc_unlock();
return ret;
}
