REGLIST_INST ("loadm", 0x324),
REGLIST_INST ("loadma", 0x325),
REGLIST_INST ("popa", 0x325),
REGLIST_INST ("storm", 0x344),
REGLIST_INST ("storma", 0x345),
/* Create a branch instruction. */
#define BR_INST(NAME, OPC1, OPC2, INS_TYPE) \
/* opc12 r disps17 */ \
{NAME, 2, OPC1, 20, INS_TYPE | RELAXABLE, {{regr,16}, {d17,0}}}, \
/* opc12 r disps33 */ \
{NAME, 3, OPC2, 20, INS_TYPE | RELAXABLE, {{regr,16}, {d33,0}}}
BR_INST ("bal", 0x307, 0x317, 0),
/* Decrement and Branch instructions. */
BR_INST ("dbnzb", 0x304, 0x314, DCR_BRANCH_INS),
BR_INST ("dbnzw", 0x305, 0x315, DCR_BRANCH_INS),
BR_INST ("dbnzd", 0x306, 0x316, DCR_BRANCH_INS),
/* Jump and link instructions. */
REG1_INST ("jal", 0xFF8),
REG2_INST ("jal", 0x37),
REG2_INST ("jalid", 0x33),
/* Create a CO-processor instruction. */
#define COP_INST(NAME, OPC, TYPE, REG1, REG2) \
/* opc12 c4 opc8 REG1 REG2 */ \
{NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{i4,16}, {REG1,4}, {REG2,0}}}
/* MULTIPLY INSTRUCTIONS */
REG3_INST ("macqw", 0x0014d),
REG3_INST ("macuw", 0x0014e),
REG3_INST ("macsw", 0x0014f),
/* Create a branch instruction. */
#define BR_INST(NAME, OPC) \
/* opc12 ra disps25 */ \
{NAME, 2, OPC, 24, NO_TYPE_INS, {{rra,0}, {disps25,0}}}
#define BR_INST_RP(NAME, OPC) \
/* opc8 rp disps25 */ \
{NAME, 3, OPC, 12, NO_TYPE_INS, {{regp,4}, {disps25,16}}}
BR_INST ("bal", 0xC0),
BR_INST_RP ("bal", 0x00102),
#define REGPP2_INST(NAME, OPC) \
/* opc16 rp rp */ \
{NAME, 2, OPC, 12, NO_TYPE_INS, {{regp,0}, {regp,4}}}
/* Jump and link instructions. */
REGP1_INST ("jal",0x00D),
REGPP2_INST ("jal",0x00148),
/* Instructions including a register list (opcode is represented as a mask). */
#define REGLIST_INST(NAME, OPC, TYPE) \
/* opc7 r count3 RA */ \
{NAME,1, (OPC<<1)+1, 23, TYPE, {{uimm3_1,20},{regr,16},{regr,0}}}, \
/* opc8 r count3 */ \
