/** * @brief Initializes the SDRAM device. * @retval SDRAM status */ void BSP_SDRAM_Init(void) { SDRAM_HandleTypeDef sdramHandle; FMC_SDRAM_TimingTypeDef Timing; /* SDRAM device configuration */ sdramHandle.Instance = FMC_SDRAM_DEVICE; /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */ Timing.LoadToActiveDelay = 2; Timing.ExitSelfRefreshDelay = 7; Timing.SelfRefreshTime = 4; Timing.RowCycleDelay = 7; Timing.WriteRecoveryTime = 2; Timing.RPDelay = 2; Timing.RCDDelay = 2; sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; /* SDRAM controller initialization */ BSP_SDRAM_MspInit(&sdramHandle); _HAL_SDRAM_Init(&sdramHandle, &Timing); /* SDRAM initialization sequence */ BSP_SDRAM_Initialization_sequence(&sdramHandle, REFRESH_COUNT); }
/** * @brief Initializes the SDRAM device. * @retval SDRAM status */ uint8_t stm32_sdram_init(sdram_config_t *config) { static uint8_t sdramstatus = SDRAM_ERROR; static DMA_HandleTypeDef dma_handle; /* SDRAM device configuration */ sdramHandle.Instance = FMC_SDRAM_DEVICE; /* Timing configuration for 100Mhz as SDRAM clock frequency (System clock is up to 200Mhz) */ FMC_SDRAM_TimingTypeDef Timing; Timing.LoadToActiveDelay = 2; Timing.ExitSelfRefreshDelay = 7; Timing.SelfRefreshTime = 4; Timing.RowCycleDelay = 7; Timing.WriteRecoveryTime = 2; Timing.RPDelay = 2; Timing.RCDDelay = 2; sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; sdramHandle.Init.ColumnBitsNumber = GetColumnBitsNumber(config); sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; sdramHandle.Init.MemoryDataWidth = GetMemoryWidth(config); sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; sdramHandle.Init.CASLatency = GetCasLatencyFMC(config); sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; sdramHandle.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; /* Enable FMC clock */ __HAL_RCC_FMC_CLK_ENABLE(); /* Enable chosen DMAx clock */ __DMAx_CLK_ENABLE(); /* SDRAM GPIO initialization */ stm_sdram_GPIO_init(); /* Configure common DMA parameters */ dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; dma_handle.Init.MemInc = DMA_MINC_ENABLE; dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; dma_handle.Init.Mode = DMA_NORMAL; dma_handle.Init.Priority = DMA_PRIORITY_HIGH; dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; dma_handle.Instance = SDRAM_DMAx_STREAM; /* Associate the DMA handle */ __HAL_LINKDMA(&sdramHandle, hdma, dma_handle); /* Deinitialize the stream for new transfer */ HAL_DMA_DeInit(&dma_handle); /* Configure the DMA stream */ HAL_DMA_Init(&dma_handle); #if 0 /* NVIC configuration for DMA transfer complete interrupt */ HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); #endif if (HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) { sdramstatus = SDRAM_ERROR; } else { sdramstatus = SDRAM_OK; } /* SDRAM initialization sequence */ BSP_SDRAM_Initialization_sequence(REFRESH_COUNT, GetCasLatencyModeReg(config)); return sdramstatus; }