void BX_CPU_C::BSR_GqEq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, op2_64; /* op2_64 is a register or memory reference */ if (i->modC0()) { op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_virtual_qword(i->seg(), RMAddr(i), &op2_64); } if (op2_64 == 0) { assert_ZF(); /* op1_64 undefined */ return; } op1_64 = 63; while ( (op2_64 & BX_CONST64(0x8000000000000000)) == 0 ) { op1_64--; op2_64 <<= 1; } SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_BITSCAN64); /* now write result back to destination */ BX_WRITE_64BIT_REG(i->nnn(), op1_64); }
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_RRX(bxInstruction_c *i) { Bit64u val64 = BX_READ_64BIT_REG(i->rm()); BX_WRITE_64BIT_REG(i->rm(), bx_bswap64(val64)); BX_NEXT_INSTR(i); }
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_GqMq(bxInstruction_c *i) { bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i)); Bit64u val64 = read_virtual_qword(i->seg(), eaddr); BX_WRITE_64BIT_REG(i->nnn(), bx_bswap64(val64)); BX_NEXT_INSTR(i); }
void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EqIdR(bxInstruction_c *i) { Bit64u op1_64, op2_64 = (Bit32s) i->Id(); op1_64 = BX_READ_64BIT_REG(i->rm()); op1_64 &= op2_64; BX_WRITE_64BIT_REG(i->rm(), op1_64); SET_FLAGS_OSZAPC_LOGIC_64(op1_64); }
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EqGqR(bxInstruction_c *i) { Bit64u op1_64, op2_64; op1_64 = BX_READ_64BIT_REG(i->rm()); op2_64 = BX_READ_64BIT_REG(i->nnn()); op1_64 ^= op2_64; BX_WRITE_64BIT_REG(i->rm(), op1_64); SET_FLAGS_OSZAPC_LOGIC_64(op1_64); }
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSS_GqMp(bxInstruction_c *i) { bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i)); Bit16u ss = read_virtual_word_64(i->seg(), (eaddr + 8) & i->asize_mask()); Bit64u reg_64 = read_virtual_qword_64(i->seg(), eaddr); load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss); BX_WRITE_64BIT_REG(i->nnn(), reg_64); BX_NEXT_INSTR(i); }
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GqEqR(bxInstruction_c *i) { Bit64u op1_64, op2_64; op1_64 = BX_READ_64BIT_REG(i->nnn()); op2_64 = BX_READ_64BIT_REG(i->rm()); op1_64 ^= op2_64; /* now write result back to destination */ BX_WRITE_64BIT_REG(i->nnn(), op1_64); SET_FLAGS_OSZAPC_LOGIC_64(op1_64); }
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GqEqM(bxInstruction_c *i) { Bit64u op1_64, op2_64; BX_CPU_CALL_METHODR(i->ResolveModrm, (i)); op1_64 = BX_READ_64BIT_REG(i->nnn()); op2_64 = read_virtual_qword_64(i->seg(), RMAddr(i)); op1_64 ^= op2_64; /* now write result back to destination */ BX_WRITE_64BIT_REG(i->nnn(), op1_64); SET_FLAGS_OSZAPC_LOGIC_64(op1_64); }
void BX_CPU_C::BSWAP_RRX(bxInstruction_c *i) { Bit64u val64, b0, b1, b2, b3, b4, b5, b6, b7; val64 = BX_READ_64BIT_REG(i->opcodeReg()); b0 = val64 & 0xff; val64 >>= 8; b1 = val64 & 0xff; val64 >>= 8; b2 = val64 & 0xff; val64 >>= 8; b3 = val64 & 0xff; val64 >>= 8; b4 = val64 & 0xff; val64 >>= 8; b5 = val64 & 0xff; val64 >>= 8; b6 = val64 & 0xff; val64 >>= 8; b7 = val64; val64 = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b4<<16) | (b4<<8) | b7; BX_WRITE_64BIT_REG(i->opcodeReg(), val64); }
void BX_CPU_C::LSS_GqMp(bxInstruction_c *i) { if (i->modC0()) { BX_DEBUG(("LSS_GqMp: invalid use of LSS, must be memory reference!")); UndefinedOpcode(i); } Bit64u reg_64; Bit16u ss; read_virtual_qword(i->seg(), RMAddr(i), ®_64); read_virtual_word(i->seg(), RMAddr(i) + 8, &ss); load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss); BX_WRITE_64BIT_REG(i->nnn(), reg_64); }
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_RRX(bxInstruction_c *i) { BX_WRITE_64BIT_REG(i->rm(), pop_64()); BX_NEXT_INSTR(i); }
void BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EqR(bxInstruction_c *i) { Bit64u op1_64 = BX_READ_64BIT_REG(i->rm()); op1_64 = ~op1_64; BX_WRITE_64BIT_REG(i->rm(), op1_64); }