void main()
{
int i,img_width=IMG_WIDTH,img_height=IMG_HEIGHT;
core_id = DNUM;
CSL_tscEnable();
CACHE_setL2Size (CACHE_0KCACHE);
CACHE_setL1DSize(CACHE_L1_32KCACHE);
CACHE_disableCaching (128);
maps_info_ptr = (maps_info*)MAPS_INFO_PTR;
if(DNUM==MASTER_CORE_ID)
{
CSL_semAcquireDirect(INIT_DONE_SEM);
memset((void*)MSMC_REG_BASE,0x0,MSMC_SRAM_SIZE);
memset((void*)MAPS_INFO_PTR,0x0,0x100);
do_power_gating();
compute_num_maps();
}
memset((void*)L2_HEAP_BASE,0x0,L2_HEAP_SIZE);
for(i=0;i<ITERATIONS;i++)
{
startVal = _itoll(TSCH,TSCL);
deeplearn(img_width, img_height);
endVal = _itoll(TSCH,TSCL);
cumulative += ((endVal-startVal)/DSP_FREQ_IN_MHZ);
}
if(DNUM==MASTER_CORE_ID)
{
printf("TimeTaken %lfus\n",(cumulative/ITERATIONS));
}
cumulative=0;
}
Int main(Int argc, Char* argv[]) {
/*
// Because MSMC memory cannot be non-cacheable, a new entry is added to
// the memory map as follows:
// name origin length
// SHARED_NO_CACHE 80000000 80000000
// Cache is disabled for this new memory range
// Then a new section is created for this memory range (cf .cfg). Memory
// translation is then used to make the region beginning fall into the
// MSMCSRAM. The rest naturally falls into DDR3.
// "translate" 2MB (0x14) from 0x80000000 to 0x00c200000 using the MPAX number 3
set_MPAX(3, 0x80000, 0x00c200, 0x14, CACHEABLE);
*/
// Disable caching from 0x80000000 to 0xFFFFFFFF
if(!CACHEABLE){
int index;
for (index = 0x80; index <= 0xFF; index++) {
CACHE_disableCaching(index);
}
}
BIOS_start();
return (0);
}
void main()
{
int i,img_width=32,img_height=32;
core_id = DNUM;
CSL_tscEnable();
CACHE_setL2Size (CACHE_0KCACHE);
CACHE_setL1DSize(CACHE_L1_32KCACHE);
CACHE_disableCaching (128);
maps_info_ptr = (maps_info*)MAPS_INFO_PTR;
if(DNUM==MASTER_CORE_ID)
{
CSL_semAcquireDirect(INIT_DONE_SEM);
memset((void*)MSMC_REG_BASE,0x0,MSMC_SRAM_SIZE);
memset((void*)MAPS_INFO_PTR,0x0,0x100);
do_power_gating();
compute_num_maps();
}
memset((void*)L2_HEAP_BASE,0x0,L2_HEAP_SIZE);
for(i=0;i<ITERATIONS;i++)
{
startVal = _itoll(TSCH,TSCL);
deeplearn(in_img, img_width, img_height);
endVal = _itoll(TSCH,TSCL);
cumulative += ((endVal-startVal)/DSP_FREQ_IN_MHZ);
}
if(DNUM==MASTER_CORE_ID)
{
#ifdef FUNCTION_PROFILE
printf("%lf %lf %lf \n",(layer1/ITERATIONS),(layer2/ITERATIONS),(layer3/ITERATIONS));
printf("%lf %lf %lf %lf \n",(pad1/ITERATIONS),(conv1/ITERATIONS),(rect1/ITERATIONS),(pool1/ITERATIONS));
printf("%lf %lf %lf %lf %lf \n",(add1/ITERATIONS),(pad2/ITERATIONS),(conv2/ITERATIONS),(rect2/ITERATIONS),(pool2/ITERATIONS));
printf("%lf %lf %lf %lf %lf \n",(add2/ITERATIONS),(pad3/ITERATIONS),(conv3/ITERATIONS),(rect3/ITERATIONS),(pool3/ITERATIONS));
#else
printf("%lf us",(cumulative/ITERATIONS));
#endif
}
cumulative=0;
}
