예제 #1
0
static void p4_check_ctrs(unsigned int const cpu, 
			  struct op_msrs const * const msrs,
			  struct pt_regs * const regs)
{
	unsigned long ctr, low, high, stag, real;
	int i;

	stag = get_stagger();

	for (i = 0; i < num_counters; ++i) {
		
		if (!sysctl.ctr[i].enabled) 
			continue;

		
		real = VIRT_CTR(stag, i);

		CCCR_READ(low, high, real);
 		CTR_READ(ctr, high, real);
		if (CCCR_OVF_P(low) || CTR_OVERFLOW_P(ctr)) {
			op_do_profile(cpu, instruction_pointer(regs), IRQ_ENABLED(regs), i);
 			CTR_WRITE(oprof_data[cpu].ctr_count[i], real);
			CCCR_CLEAR_OVF(low);
			CCCR_WRITE(low, high, real);
 			CTR_WRITE(oprof_data[cpu].ctr_count[i], real);
		}
	}

	
	apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
}
예제 #2
0
void resetCounter(int counter){

	unsigned long long high_low;
				unsigned pmc, setpmc;
				switch(counter){
					case 0: pmc = IA32_PMC0;
							setpmc = IA32_PERFEVTSEL0;
							break;

					case 1: pmc = IA32_PMC1;
							setpmc = IA32_PERFEVTSEL1;
							break;
					case 2: pmc = IA32_PMC2;
							setpmc = IA32_PERFEVTSEL2;
							break;
					case 3: pmc = IA32_PMC3;
							setpmc = IA32_PERFEVTSEL3;
							break;
					default: 
					return;
						break;
				}
		rdmsrl(pmc, high_low);
		CCCR_CLEAR_OVF(high_low);
		rdmsrl(setpmc, high_low);
		setupCounter(counter, high_low & 0xff, high_low>>8 & 0xff, 0);


}
예제 #3
0
static int p4_check_ctrs(unsigned int const cpu, 
			  struct op_msrs const * const msrs,
			  struct pt_regs * const regs)
{
	unsigned long ctr, low, high, stag, real;
	int i;
	unsigned long eip = instruction_pointer(regs);
	int is_kernel = !user_mode(regs);

	stag = get_stagger();

	for (i = 0; i < num_counters; ++i) {
		
		if (!counter_config[i].event) 
			continue;

		/* 
		 * there is some eccentricity in the hardware which
		 * requires that we perform 2 extra corrections:
		 *
		 * - check both the CCCR:OVF flag for overflow and the
		 *   counter high bit for un-flagged overflows.
		 *
		 * - write the counter back twice to ensure it gets
		 *   updated properly.
		 * 
		 * the former seems to be related to extra NMIs happening
		 * during the current NMI; the latter is reported as errata
		 * N15 in intel doc 249199-029, pentium 4 specification
		 * update, though their suggested work-around does not
		 * appear to solve the problem.
		 */
		
		real = VIRT_CTR(stag, i);

		CCCR_READ(low, high, real);
 		CTR_READ(ctr, high, real);
		if (CCCR_OVF_P(low) || CTR_OVERFLOW_P(ctr)) {
			oprofile_add_sample(eip, is_kernel, i, cpu);
 			CTR_WRITE(reset_value[i], real);
			CCCR_CLEAR_OVF(low);
			CCCR_WRITE(low, high, real);
 			CTR_WRITE(reset_value[i], real);
			/* P4 quirk: you have to re-unmask the apic vector */
			apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
		}
	}

	/* P4 quirk: you have to re-unmask the apic vector */
	apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);

	/* See op_model_ppro.c */
	return 1;
}