#define CFG_SCLKCNT(div) (div<<24) /* 0xFF~0x2 */
#define CFG_RXBITS(rx) ((rx - 1)<<16) /* 0x1F~0x1 */
#define CFG_TXBITS(tx) ((tx - 1)<<8) /* 0x1F~0x1, 0x1: 2bits ... 0x1F: 32bits */
#define CFG_SPI_ENA(spi) (spi<<3)
#define CFG_SPI_SEL(spi) (spi<<2) /* 1: port1; 0: port0 */
#define CFG_SPI_3W4WB(wire) (wire<<1) /* 1: 3-wire; 0: 4-wire */
struct pxa168fb_mach_info aspenite_lcd_info __initdata = {
.id = "Base-aspen",
.modes = video_modes_aspen,
.num_modes = ARRAY_SIZE(video_modes_aspen),
.pix_fmt = PIX_FMT_RGB565,
.io_pin_allocation_mode = PIN_MODE_DUMB_24,
.dumb_mode = DUMB_MODE_RGB888,
.active = 1,
.spi_ctrl = CFG_SCLKCNT(2) | CFG_TXBITS(16) | CFG_SPI_SEL(1) | CFG_SPI_3W4WB(1) | CFG_SPI_ENA(1),
.spi_gpio_cs = GPIO_EXT1(14),
.spi_gpio_reset = -1,
.panel_rbswap = 1,
.invert_pixclock = 1,
.pxa168fb_lcd_power = tpo_lcd_power,
.max_fb_size = 1024 * 768 * 4 * 2,
.invert_pixclock = 1,
};
struct pxa168fb_mach_info aspenite_lcd_ovly_info __initdata = {
.id = "Ovly-aspen",
.modes = video_modes_aspen,
.num_modes = ARRAY_SIZE(video_modes_aspen),
.pix_fmt = PIX_FMT_RGB565,
.io_pin_allocation_mode = PIN_MODE_DUMB_24,
#define CFG_SCLKCNT(div) (div<<24) /* 0xFF~0x2 */
#define CFG_RXBITS(rx) ((rx - 1)<<16) /* 0x1F~0x1 */
#define CFG_TXBITS(tx) ((tx - 1)<<8) /* 0x1F~0x1, 0x1: 2bits ... 0x1F: 32bits */
#define CFG_SPI_ENA(spi) (spi<<3)
#define CFG_SPI_SEL(spi) (spi<<2) /* 1: port1; 0: port0 */
#define CFG_SPI_3W4WB(wire) (wire<<1) /* 1: 3-wire; 0: 4-wire */
static struct pxa910fb_mach_info u810_lcd_info __initdata = {
.id = "Base",
.modes = lead_video_modes,
.num_modes = ARRAY_SIZE(lead_video_modes),
.pix_fmt = PIX_FMT_RGB565,
.io_pin_allocation_mode = PIN_MODE_DUMB_18_SPI,
.dumb_mode = DUMB_MODE_RGB666,
.active = 1,
.spi_ctrl = CFG_SCLKCNT(16) | CFG_TXBITS(9) | CFG_SPI_SEL(1) | CFG_SPI_3W4WB(0) | CFG_SPI_ENA(1),
.spi_gpio_cs = -1,
.spi_gpio_reset = mfp_to_gpio(MFP_PIN_GPIO106),
.panel_rbswap = 1,
.pxa910fb_lcd_power = lead_lcd_power,
.invert_pixclock = 1,
.max_fb_size = 1280 * 720 * 4,
};
static struct pxa910fb_mach_info u810_lcd_ovly_info __initdata = {
.id = "Ovly",
.modes = lead_video_modes,
.num_modes = ARRAY_SIZE(lead_video_modes),
.pix_fmt = PIX_FMT_RGB565,
.io_pin_allocation_mode = PIN_MODE_DUMB_18_SPI,
.dumb_mode = DUMB_MODE_RGB666,
#define CFG_SPI_3W4WB(wire) (wire<<1)
#define LCD_ISR_CLEAR_MASK 0xffff00cc
static struct pxa168fb_mach_info truly_lcd_info = {
.id = "Base",
.modes = truly_video_modes,
.sclk_div = 0x4000000d,
.burst_len = 8,
.isr_clear_mask = LCD_ISR_CLEAR_MASK,
.num_modes = ARRAY_SIZE(truly_video_modes),
.pix_fmt = PIX_FMT_RGB888PACK,
.io_pin_allocation_mode = PIN_MODE_DUMB_24,
.dumb_mode = DUMB_MODE_RGB888,
.active = 1,
.spi_ctrl = CFG_SCLKCNT(32) | CFG_TXBITS(9) |
CFG_SPI_3W4WB(1) | CFG_SPI_ENA(1),
.spi_gpio_cs = GPIO_EXT0(5),
.spi_gpio_reset = GPIO_EXT0(3),
.pxa168fb_lcd_power = truly_lcd_power,
.invert_pixclock = 1,
.panel_rbswap = 1,
.max_fb_size = 800 * 480 * 8,
};
static struct pxa168fb_mach_info truly_lcd_ovly_info = {
.id = "Ovly",
.modes = truly_video_modes,
.num_modes = ARRAY_SIZE(truly_video_modes),
.pix_fmt = PIX_FMT_RGB888PACK,
.io_pin_allocation_mode = PIN_MODE_DUMB_24,