DEF_CLK(SYS_OST, GATE(20)), DEF_CLK(PDMA, GATE(21)), DEF_CLK(CIM, GATE(22) | PARENT(LCD)), DEF_CLK(LCD, GATE(23)), DEF_CLK(AES, GATE(24)), DEF_CLK(MAC, GATE(25)), DEF_CLK(PCM, GATE(26)), DEF_CLK(RTC, GATE(27)), DEF_CLK(APB0, GATE(28)), DEF_CLK(AHB0, GATE(29)), DEF_CLK(CPU, GATE(30)), DEF_CLK(DDR, GATE(31)), DEF_CLK(WDT, TCU_WDT(0)), DEF_CLK(CGU_MSC_MUX, CGU(CGU_MSC_MUX)), DEF_CLK(CGU_PCM, CGU_AUDIO(CGU_AUDIO_PCM)), DEF_CLK(CGU_CIM, CGU(CGU_CIM)), DEF_CLK(CGU_SFC, CGU(CGU_SFC)), DEF_CLK(CGU_USB, CGU(CGU_USB)), DEF_CLK(CGU_MSC1, CGU(CGU_MSC1)| PARENT(CGU_MSC_MUX)), DEF_CLK(CGU_MSC0, CGU(CGU_MSC0)| PARENT(CGU_MSC_MUX)), DEF_CLK(CGU_LCD, CGU(CGU_LCD)), DEF_CLK(CGU_I2S, CGU_AUDIO(CGU_AUDIO_I2S)), DEF_CLK(CGU_MACPHY, CGU(CGU_MACPHY)), DEF_CLK(CGU_DDR, CGU(CGU_DDR)), #undef GATE #undef CPCCR #undef CGU #undef CGU_AUDIO #undef PARENT
DEF_CLK(IPU, GATE(32 + 2)),
DEF_CLK(GMAC, GATE(32 + 4)),
DEF_CLK(AES, GATE(32 + 5)),
DEF_CLK(AHB0, GATE(32 + 10)),
DEF_CLK(SYS_OST, GATE(32 + 11)),
DEF_CLK(APB0, GATE(32 + 14)),
DEF_CLK(CPU, GATE(32 + 15)),
[CLK_ID_CGU] = {.name = "noclk", 1},
DEF_CLK(CGU_MSC_MUX, CGU(CGU_MSC_MUX)),
DEF_CLK(CGU_ISP, CGU(CGU_ISP)),
DEF_CLK(CGU_CIM, CGU(CGU_CIM)),
DEF_CLK(CGU_SSI, CGU(CGU_SSI)),
DEF_CLK(CGU_I2S, CGU(CGU_I2S)),
DEF_CLK(CGU_MSC1, CGU(CGU_MSC1)| PARENT(H2CLK)),
DEF_CLK(CGU_MSC0, CGU(CGU_MSC0)| PARENT(H2CLK)),
DEF_CLK(CGU_MACPHY, CGU(CGU_MACPHY)),
DEF_CLK(CGU_VPU, CGU(CGU_VPU)),
DEF_CLK(CGU_DDR, CGU(CGU_DDR)),
#undef GATE
#undef CPCCR
#undef CGU
#undef PARENT
#undef DEF_CLK
};
static int cgu_set_rate(struct clk *clk, unsigned long rate){
if(strncmp(clk->name,"cgu_msc",7))
DEF_CLK(DES, GATE(28) | PARENT(PCLK)), DEF_CLK(RTC, GATE(29) | PARENT(EXT0)), DEF_CLK(TCU, GATE(30) | PARENT(PCLK)), DEF_CLK(DDR, GATE(31) | PARENT(PCLK)), DEF_CLK(VPU0, GATE(32 + 0) | PARENT(PCLK)), DEF_CLK(IPU, GATE(32 + 2) | PARENT(PCLK)), DEF_CLK(GMAC, GATE(32 + 4) | PARENT(PCLK)), DEF_CLK(AES, GATE(32 + 5) | PARENT(PCLK)), DEF_CLK(AHB0, GATE(32 + 10)), DEF_CLK(SYS_OST, GATE(32 + 11)), DEF_CLK(APB0, GATE(32 + 14)), DEF_CLK(CPU, GATE(32 + 15)), DEF_CLK(CGU_MSC_MUX, CGU(CGU_MSC_MUX)), DEF_CLK(CGU_ISP, CGU(CGU_ISP)), DEF_CLK(CGU_CIM, CGU(CGU_CIM)), DEF_CLK(CGU_SSI, CGU(CGU_SSI)), DEF_CLK(CGU_I2S, CGU(CGU_I2S)), DEF_CLK(CGU_MSC1, CGU(CGU_MSC1) | PARENT(CGU_MSC_MUX)), DEF_CLK(CGU_MSC0, CGU(CGU_MSC0) | PARENT(CGU_MSC_MUX)), DEF_CLK(CGU_LPC, CGU(CGU_LPC)), DEF_CLK(CGU_VPU, CGU(CGU_VPU)), DEF_CLK(CGU_DDR, CGU(CGU_DDR)), DEF_CLK(CGU_MACPHY, CGU(CGU_MACPHY)), #undef GATE #undef CPCCR #undef CGU #undef PWC #undef PARENT
