/** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE and PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval None */ void HAL_RCC_DeInit(void) { /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO); /* Reset HSEON, CSSON, PLLON bits */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); /* Reset CFGR3 register */ CLEAR_REG(RCC->CFGR3); /* Disable all interrupts */ CLEAR_REG(RCC->CIR); }
/** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - MSI ON and used as system clock source * - HSI, HSE and PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS and MCO1 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval None */ void HAL_RCC_DeInit(void) { /* Set MSION bit */ SET_BIT(RCC->CR, RCC_CR_MSION); /* Switch SYSCLK to MSI*/ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); /* Reset HSION, HSEON, CSSON, HSEBYP & PLLON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_HSEBYP); /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); /* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */ MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << POSITION_VAL(RCC_ICSCR_MSITRIM)) | RCC_ICSCR_MSIRANGE_5)); /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_ICSCR_HSITRIM))); /* Disable all interrupts */ CLEAR_REG(RCC->CIR); /* Update the SystemCoreClock global variable */ SystemCoreClock = MSI_VALUE; }
/** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - MSI ON and used as system clock source (MSI range is not modified * - by this function, it keep the value configured by user application) * - HSI, HSE and PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS and MCO OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * @note -Peripheral clocks * @note -HSI48, LSI, LSE and RTC clocks * @param None * @retval None */ void HAL_RCC_DeInit(void) { /* Set MSION bit */ SET_BIT(RCC->CR, RCC_CR_MSION); /* Reset HSION, HSEON, CSSON, PLLON */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_CSSHSEON | RCC_CR_PLLON); /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); /* Disable all interrupts */ CLEAR_REG(RCC->CIER); }
/** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE and PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS and MCO1 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval None */ __weak void HAL_RCC_DeInit(void) { /* Switch SYSCLK to HSI */ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); /* Reset HSEON, CSSON, & PLLON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM))); /* Disable all interrupts */ CLEAR_REG(RCC->CIR); }