static int aml_bl_update_status(struct backlight_device *bd)
{
struct aml_bl *amlbl = bl_get_data(bd);
int brightness = bd->props.brightness;
#ifdef CONFIG_ARCH_MESON6
static int led_pwm_off = 0;
#endif
DPRINT("%s() brightness=%d\n", __FUNCTION__, brightness);
DPRINT("%s() pdata->set_bl_level=%p\n", __FUNCTION__, amlbl->pdata->set_bl_level);
/*
if (bd->props.power != FB_BLANK_UNBLANK)
brightness = 0;
if (bd->props.fb_blank != FB_BLANK_UNBLANK)
brightness = 0;
*/
if (brightness < 0)
brightness = 0;
else if (brightness > 255)
brightness = 255;
#ifdef CONFIG_ARCH_MESON6
if (led_pwm_off && brightness > 0) {
switch_mod_gate_by_type(MOD_LED_PWM, 1);
led_pwm_off = 0;
}
#endif /* CONFIG_ARCH_MESON6 */
#ifndef CONFIG_MESON_CS_DCDC_REGULATOR
if ((brightness > 0) && (0 == IS_CLK_GATE_ON(VGHL_PWM))) {
CLK_GATE_ON(VGHL_PWM);
DPRINT("%s() CLK_GATE_ON(VGHL_PWM)\n", __FUNCTION__);
}
#endif
if (amlbl->pdata->set_bl_level)
amlbl->pdata->set_bl_level(brightness);
#ifndef CONFIG_MESON_CS_DCDC_REGULATOR
if ((brightness == 0) && (IS_CLK_GATE_ON(VGHL_PWM))) {
CLK_GATE_OFF(VGHL_PWM);
DPRINT("%s() CLK_GATE_OFF(VGHL_PWM)\n", __FUNCTION__);
}
#endif
#ifdef CONFIG_ARCH_MESON6
if (brightness == 0) {
switch_mod_gate_by_type(MOD_LED_PWM, 0);
led_pwm_off = 1;
}
#endif /* CONFIG_ARCH_MESON6 */
return 0;
}
static int audiodsp_open(struct inode *node, struct file *file)
{
DSP_PRNT("dsp_open\n");
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
CLK_GATE_ON(AHB_BRIDGE);
#endif
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_MEDIA_CPU, 1);
/* Audio DSP firmware uses mailbox registers for communications
* with host processor. And these mailbox registers unfortunately
* falls into the assistant module, which is in vdec DOS clock domain.
* So we have to make sure the clock domain is enabled/disabled when
* audio firmware start/stop running.
* Note the module_gating has ref count so a flag 0 does
* not mean the vdec clock is gated off immediately.
*/
switch_mod_gate_by_type(MOD_VDEC, 1);
#endif
audiodsp_prevent_sleep();
return 0;
}
int tvoutc_setmode(tvmode_t mode)
{
const reg_t *s;
const tvinfo_t * tvinfo;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
static int uboot_display_flag = 1;
#else
static int uboot_display_flag = 0;
#endif
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
mutex_lock(&setmode_mutex);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
//TODO
// switch_mod_gate_by_name("venc", 1);
#endif
tvinfo = tvinfo_mode(mode);
if(!tvinfo) {
printk(KERN_ERR "tvinfo %d not find\n", mode);
mutex_unlock(&setmode_mutex);
return 0;
}
printk("TV mode %s selected.\n", tvinfo->id);
#ifdef CONFIG_ARCH_MESON8B
if( (mode!=TVMODE_480CVBS) && (mode!=TVMODE_576CVBS) )
{
CLK_GATE_OFF(CTS_VDAC);
CLK_GATE_OFF(DAC_CLK);
}
if( (mode!=TVMODE_480I) && (mode!=TVMODE_480CVBS) &&
(mode!=TVMODE_576I) && (mode!=TVMODE_576CVBS) )
{
CLK_GATE_OFF(CTS_ENCI);
CLK_GATE_OFF(VCLK2_ENCI);
CLK_GATE_OFF(VCLK2_VENCI1);
}
#endif
s = tvregs_setting_mode(mode);
if(!s) {
printk("display mode %d regs setting failed\n", mode);
mutex_lock(&setmode_mutex);
return 0;
}
//s = tvregsTab[mode];
if(uboot_display_flag) {
uboot_display_flag = 0;
if(uboot_display_already(mode)) {
printk("already display in uboot\n");
mutex_unlock(&setmode_mutex);
return 0;
}
}
#if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8)
// for hdmi mode, disable HPLL as soon as possible
if( (mode==TVMODE_480I) || (mode==TVMODE_480P) ||
(mode==TVMODE_576I) || (mode==TVMODE_576P) ||
(mode==TVMODE_720P) || (mode==TVMODE_720P_50HZ) ||
(mode==TVMODE_1080I) || (mode==TVMODE_1080I_50HZ) ||
(mode==TVMODE_1080P) || (mode==TVMODE_1080P_50HZ) ||
(mode==TVMODE_1080P_24HZ) || (mode==TVMODE_4K2K_24HZ) ||
(mode==TVMODE_4K2K_25HZ) || (mode==TVMODE_4K2K_30HZ) || (mode==TVMODE_4K2K_FAKE_5G) ||
(mode==TVMODE_4K2K_SMPTE) || (mode==TVMODE_4K2K_60HZ) )
{
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV
// NOTE: for G9TV, DO NOT TURN OFF HPLL
#else
WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 0x0, 30, 1);
#endif
}
cvbs_cntl_output(0);
#endif
while (MREG_END_MARKER != s->reg)
setreg(s++);
printk("%s[%d]\n", __func__, __LINE__);
#ifdef CONFIG_CVBS_PERFORMANCE_COMPATIBLITY_SUPPORT
cvbs_performance_enhancement(mode);
#endif
if(mode >= TVMODE_VGA && mode <= TVMODE_FHDVGA){ //set VGA pinmux
aml_write_reg32(P_PERIPHS_PIN_MUX_0, (aml_read_reg32(P_PERIPHS_PIN_MUX_0)|(3<<20)));
}else{
aml_write_reg32(P_PERIPHS_PIN_MUX_0, (aml_read_reg32(P_PERIPHS_PIN_MUX_0)&(~(3<<20))));
}
printk("%s[%d] mode is %d\n", __func__, __LINE__, mode);
#if ((defined CONFIG_ARCH_MESON8) || (defined CONFIG_ARCH_MESON8B))
// for hdmi mode, leave the hpll setting to be done by hdmi module.
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
set_tvmode_misc(mode);
#else
set_tvmode_misc(mode);
#endif
#ifdef CONFIG_ARCH_MESON1
tvoutc_setclk(mode);
printk("%s[%d]\n", __func__, __LINE__);
enable_vsync_interrupt();
#endif
#ifdef CONFIG_AM_TV_OUTPUT2
switch(mode)
{
case TVMODE_480I:
case TVMODE_480I_RPT:
case TVMODE_480CVBS:
case TVMODE_576I:
case TVMODE_576I_RPT:
case TVMODE_576CVBS:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 0, 2); //reg0x271a, select ENCI to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 4, 4); //reg0x271a, Select encI clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 8, 4); //reg0x271a,Enable VIU of ENC_I domain to VDIN;
break;
case TVMODE_480P:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_480P_59HZ:
#endif
case TVMODE_480P_RPT:
case TVMODE_576P:
case TVMODE_576P_RPT:
case TVMODE_720P:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_720P_59HZ:
#endif
case TVMODE_720P_50HZ:
case TVMODE_1080I: //??
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_1080I_59HZ:
#endif
case TVMODE_1080I_50HZ: //??
case TVMODE_1080P:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_1080P_59HZ:
#endif
case TVMODE_1080P_50HZ:
case TVMODE_1080P_24HZ:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_1080P_23HZ:
#endif
case TVMODE_4K2K_30HZ:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_4K2K_29HZ:
#endif
case TVMODE_4K2K_25HZ:
case TVMODE_4K2K_24HZ:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_4K2K_23HZ:
#endif
case TVMODE_4K2K_SMPTE:
case TVMODE_4K2K_FAKE_5G:
case TVMODE_4K2K_60HZ:
case TVMODE_VGA:
case TVMODE_SVGA:
case TVMODE_XGA:
case TVMODE_SXGA:
case TVMODE_WSXGA:
case TVMODE_FHDVGA:
default:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 0, 2); //reg0x271a, select ENCP to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 4, 4); //reg0x271a, Select encP clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 8, 4); //reg0x271a,Enable VIU of ENC_P domain to VDIN;
break;
}
#endif
aml_write_reg32(P_VPP_POSTBLEND_H_SIZE, tvinfo->xres);
#ifdef CONFIG_ARCH_MESON3
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
#ifdef CONFIG_ARCH_MESON6
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
{
msleep(1000);
if(get_power_level() == 0) {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x5);
} else {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x7);
}
} else {
if(get_power_level() == 0) {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x0);
} else {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x7);
}
}
#endif
#if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8)
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
{
msleep(1000);
CLK_GATE_ON(VCLK2_ENCI);
CLK_GATE_ON(VCLK2_VENCI1);
CLK_GATE_ON(CTS_ENCI);
CLK_GATE_ON(CTS_VDAC);
CLK_GATE_ON(DAC_CLK);
cvbs_cntl_output(1);
}
#endif
//while(1);
mutex_unlock(&setmode_mutex);
return 0;
}
void sd_resume(struct memory_card *card)
{
printk("***Entered %s:%s\n", __FILE__,__func__);
CLK_GATE_ON(SDIO);
}
void sii5293_start_vdin(sii5293_vdin *info, int width, int height, int frame_rate, int field_flag)
{
vdin_parm_t para;
printk("[%s]-%.3d, width = %d, height = %d, frame_rate = %d, field_flag = %d\n",
__FUNCTION__, __LINE__, width,height,frame_rate,field_flag);
// printk("[%s]-%.3d, info = 0x%x\n",__FUNCTION__, __LINE__, info);
if(info->vdin_started)
{
//printk("[%s]-%.3d, info->vdin_info = 0x%x\n",__FUNCTION__, __LINE__, &(info->vdin_info) );
if( (info->vdin_info.cur_width != width) || (info->vdin_info.cur_height != height) ||
(info->vdin_info.cur_frame_rate != frame_rate) )
{
stop_tvin_service(0);
CLK_GATE_OFF(MISC_DVIN);
info->vdin_started=0;
printk("%s: stop vdin\n", __func__);
}
}
CLK_GATE_ON(MISC_DVIN);
if( (info->vdin_started==0) && (width>0) && (height>0) && (frame_rate>0) )
{
int start_pix=138, start_line_o=22, start_line_e=23, h_total=1728, v_total=625;
info->vdin_info.cur_width = width;
info->vdin_info.cur_height = height;
info->vdin_info.cur_frame_rate = frame_rate;
if(field_flag && height <= 576 )
{
// for rgb 576i signal from 9233, it's 720/864, not 1440/1728
if( (width==720)&&(height==288) )
{
start_pix = 138;
start_line_o = 22;
start_line_e = 23;
h_total = 1728;
v_total = 625;
}
// for rgb 480i signal from 9233, it's 720/858, not 1440/1716
else if( (width==720)&&(height==240) )
{
start_pix = 114;
start_line_o = 18;
start_line_e = 19;
h_total = 1716;
v_total = 525;
}
sii5293_config_dvin(1, //hs_pol_inv,
1, //vs_pol_inv,
0, //de_pol_inv,
0, //field_pol_inv,
0, //ext_field_sel,
3, //de_mode,
0, //data_comp_map,
0, //mode_422to444,
0, //dvin_clk_inv,
0, //vs_hs_tim_ctrl,
400, //hs_lead_vs_odd_min,
1200, //hs_lead_vs_odd_max,
start_pix,//sii_get_hs_backporch()*2,//0xdc, //active_start_pix_fe,
start_pix,//sii_get_hs_backporch()*2,//0xdc, //active_start_pix_fo,
start_line_e,//sii_get_vs_backporch(), //0x19, //active_start_line_fe,
start_line_o,//sii_get_vs_backporch(),//0x19, //active_start_line_fo,
h_total,//sii_get_h_total(), //0x672, //line_width,
v_total//sii_get_v_total()*2 //0x2ee //field_height
);
}
else
{
sii5293_config_dvin(height>576?0:1, //hs_pol_inv,
height>576?0:1, //vs_pol_inv,
0, //de_pol_inv,
(field_flag && height>=540)?1:0, //field_pol_inv, set to 1 for 1080i
0, //ext_field_sel,
3, //de_mode,
0, //data_comp_map,
0, //mode_422to444,
0, //dvin_clk_inv,
0, //vs_hs_tim_ctrl,
0, //hs_lead_vs_odd_min,
0, //hs_lead_vs_odd_max,
sii_get_hs_backporch(),//0xdc, //active_start_pix_fe,
sii_get_hs_backporch(),//0xdc, //active_start_pix_fo,
sii_get_vs_backporch(), //0x19, //active_start_line_fe,
sii_get_vs_backporch(),//0x19, //active_start_line_fo,
sii_get_h_total(), //0x672, //line_width,
sii_get_v_total() //0x2ee //field_height
);
}
memset( ¶, 0, sizeof(para));
para.port = TVIN_PORT_DVIN0;
para.frame_rate = frame_rate;
para.h_active = info->vdin_info.cur_width;
para.v_active = info->vdin_info.cur_height;
if(field_flag){
if(info->vdin_info.cur_width == 1920 &&
(info->vdin_info.cur_height == 1080 || info->vdin_info.cur_height == 540)){
if( frame_rate == 60 )
para.fmt = TVIN_SIG_FMT_HDMI_1920X1080I_60HZ;
else if( frame_rate == 50 )
para.fmt = TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_A;
para.v_active = 1080;
}
/*
else if( info->vdin_info.cur_width == 720 && (info->vdin_info.cur_height == 576 || info->vdin_info.cur_height == 288)){
para.fmt = TVIN_SIG_FMT_HDMI_720X576I_50HZ;
para.v_active = 576;
set_invert_top_bot(true);
}
*/
else if(info->vdin_info.cur_width == 720 &&
(info->vdin_info.cur_height == 576 || info->vdin_info.cur_height == 288)){
para.fmt = TVIN_SIG_FMT_MAX;//TVIN_SIG_FMT_HDMI_1440X576I_50HZ;
para.v_active = 288;
set_invert_top_bot(true);
}
/*
else if( info->vdin_info.cur_width == 720 && (info->vdin_info.cur_height == 480 || info->vdin_info.cur_height == 240)){
para.fmt = TVIN_SIG_FMT_HDMI_720X480I_60HZ;
para.v_active = 480;
set_invert_top_bot(true);
}
*/
else if(info->vdin_info.cur_width == 720 &&
(info->vdin_info.cur_height == 480 || info->vdin_info.cur_height == 240)){
para.fmt = TVIN_SIG_FMT_MAX;//TVIN_SIG_FMT_HDMI_1440X480I_60HZ;
para.v_active = 240;
set_invert_top_bot(true);
}
else{
para.fmt = TVIN_SIG_FMT_MAX+1;
set_invert_top_bot(true);
}
para.scan_mode = TVIN_SCAN_MODE_INTERLACED;
}
else{
if(info->vdin_info.cur_width == 1920 && info->vdin_info.cur_height == 1080){
if( info->vdin_info.cur_frame_rate == 60 )
para.fmt = TVIN_SIG_FMT_HDMI_1920X1080P_60HZ;
else if( info->vdin_info.cur_frame_rate == 30 )
para.fmt = TVIN_SIG_FMT_MAX;//TVIN_SIG_FMT_HDMI_1920X1080P_30HZ;
}
else if(info->vdin_info.cur_width == 1280 && info->vdin_info.cur_height == 720){
para.fmt = TVIN_SIG_FMT_HDMI_1280X720P_60HZ;
}
else if((info->vdin_info.cur_width == 1440 || info->vdin_info.cur_width == 720) && info->vdin_info.cur_height == 576){
para.fmt = TVIN_SIG_FMT_HDMI_720X576P_50HZ;
}
else if((info->vdin_info.cur_width == 1440 || info->vdin_info.cur_width == 720) && info->vdin_info.cur_height == 480){
para.fmt = TVIN_SIG_FMT_HDMI_720X480P_60HZ;
}
else{
para.fmt = TVIN_SIG_FMT_MAX+1;
}
para.scan_mode = TVIN_SCAN_MODE_PROGRESSIVE;
}
para.hsync_phase = 1;
para.vsync_phase = 0;
//para.hs_bp = 0;
//para.vs_bp = 2;
para.cfmt = TVIN_RGB444;
para.dfmt = TVIN_YUV422;
para.reserved = 0; //skip_num
printk("[%s] begin start_tvin_service() !\n",__FUNCTION__);
#ifdef HDMIIN_FRAME_SKIP_MECHANISM
if( (SKIP_STATUS_NORMAL==flag_skip_status) ||
(SKIP_STATUS_STANDBY==flag_skip_status) ||
(SKIP_STATUS_CABLE==flag_skip_status) )
flag_skip_enable = 1;
#endif
start_tvin_service(0,¶);
info->vdin_started = 1;
//printk("%s: %dx%d %d %d/s\n", __func__, width, height, frame_rate, field_flag);
}
return ;
}
static void amvdec_pg_enable(bool enable)
{
ulong timeout;
if (enable) {
CLK_GATE_ON(MDEC_CLK_PIC_DC);
CLK_GATE_ON(MDEC_CLK_DBLK);
CLK_GATE_ON(MC_CLK);
CLK_GATE_ON(IQIDCT_CLK);
//CLK_GATE_ON(VLD_CLK);
CLK_GATE_ON(AMRISC);
} else {
CLK_GATE_OFF(AMRISC);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(MDEC_PIC_DC_STATUS) != 0) {
if (time_after(jiffies, timeout)) {
WRITE_MPEG_REG_BITS(MDEC_PIC_DC_CTRL, 1, 0, 1);
WRITE_MPEG_REG_BITS(MDEC_PIC_DC_CTRL, 0, 0, 1);
READ_MPEG_REG(MDEC_PIC_DC_STATUS);
READ_MPEG_REG(MDEC_PIC_DC_STATUS);
READ_MPEG_REG(MDEC_PIC_DC_STATUS);
break;
}
}
CLK_GATE_OFF(MDEC_CLK_PIC_DC);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(DBLK_STATUS) & 1) {
if (time_after(jiffies, timeout)) {
WRITE_MPEG_REG(DBLK_CTRL, 3);
WRITE_MPEG_REG(DBLK_CTRL, 0);
READ_MPEG_REG(DBLK_STATUS);
READ_MPEG_REG(DBLK_STATUS);
READ_MPEG_REG(DBLK_STATUS);
break;
}
}
CLK_GATE_OFF(MDEC_CLK_DBLK);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(MC_STATUS0) & 1) {
if (time_after(jiffies, timeout)) {
SET_MPEG_REG_MASK(MC_CTRL1, 0x9);
CLEAR_MPEG_REG_MASK(MC_CTRL1, 0x9);
READ_MPEG_REG(MC_STATUS0);
READ_MPEG_REG(MC_STATUS0);
READ_MPEG_REG(MC_STATUS0);
break;
}
}
CLK_GATE_OFF(MC_CLK);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(DCAC_DMA_CTRL) & 0x8000) {
if (time_after(jiffies, timeout)) {
break;
}
}
WRITE_MPEG_REG(RESET0_REGISTER, 4);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
CLK_GATE_OFF(IQIDCT_CLK);
//CLK_GATE_OFF(VLD_CLK);
}
}
void ee_gate_on(void)
{
printf("ee_gate_on ...\n");
/*
//if close , audio maybe have noise
CLK_GATE_ON(AUD);
CLK_GATE_ON(AUD2);
CLK_GATE_ON(AUD_CLK_2);
CLK_GATE_ON(AUD_CLK_3);
*/
CLK_GATE_ON(AUD_IN);
CLK_GATE_ON(AIU_AUD_MIXER);
CLK_GATE_ON(SANA);
/*kernel will reopen */
CLK_GATE_ON(CTS_ENCL);
/* CLK_GATE_ON(CTS_ENCT); */
CLK_GATE_ON(CTS_ENCI);
/* CLK_GATE_ON(CTS_ENCP); */
/*close cvbs clock*/
CLK_GATE_ON(DAC_CLK);
CLK_GATE_ON(CTS_VDAC);
/* usb clock close */
CLK_GATE_ON(USB0);
CLK_GATE_ON(USB1);
CLK_GATE_ON(USB_CLK);
CLK_GATE_ON(MISC_USB0_TO_DDR);
CLK_GATE_ON(MISC_USB1_TO_DDR);
/* uarts close */
CLK_GATE_ON(UART0);
CLK_GATE_ON(UART1);
CLK_GATE_ON(UART2);
CLK_GATE_ON(UART3);
CLK_GATE_ON(VCLK2_VENCP);
CLK_GATE_ON(VCLK2_VENCT);
CLK_GATE_ON(VCLK2_VENCT1);
CLK_GATE_ON(VCLK2_OTHER);
CLK_GATE_ON(VCLK2_VENCI);
CLK_GATE_ON(VCLK2_VENCI1);
CLK_GATE_ON(VCLK2_VENCL);
CLK_GATE_ON(VCLK2_OTHER1);
CLK_GATE_ON(VCLK2_ENCI);
CLK_GATE_ON(VCLK2_ENCL);
CLK_GATE_ON(VCLK2_ENCT);
CLK_GATE_ON(VDEC_CLK_1);
CLK_GATE_ON(VDEC_CLK_2);
CLK_GATE_ON(VDEC2_CLK_1);
CLK_GATE_ON(VDEC2_CLK_2);
CLK_GATE_ON(HCODEC_CLK_1);
CLK_GATE_ON(HCODEC_CLK_2);
/* CLK_GATE_ON(HEVC_CLK_1 ); */
/* CLK_GATE_ON(HEVC_CLK_2 ); */
CLK_GATE_ON(MMC_A_PCLK);
CLK_GATE_ON(MMC_B_PCLK);
CLK_GATE_ON(MMC_C_PCLK);
CLK_GATE_ON(LCD_AN_PHY2);
CLK_GATE_ON(LCD_AN_PHY3);
CLK_GATE_ON(ETHERNET);
CLK_GATE_ON(ETH_CLK);
CLK_GATE_ON(GE2D);
CLK_GATE_ON(GEN_CLK);
CLK_GATE_ON(PCM_MCLK);
CLK_GATE_ON(PCM_SCLK);
CLK_GATE_ON(HIU_PARSER_TOP);
/*************************/
CLK_GATE_ON(AHB_ARB0);
CLK_GATE_ON(ASYNC_FIFO);
CLK_GATE_ON(STREAM);
CLK_GATE_ON(RANDOM_NUM_GEN);
CLK_GATE_ON(RANDOM_NUM_GEN1);
CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN);
CLK_GATE_ON(I2C);
CLK_GATE_ON(SPI);
CLK_GATE_ON(SPICC);
CLK_GATE_ON(DOS);
CLK_GATE_ON(SAR_ADC);
CLK_GATE_ON(MISC_DVIN);
CLK_GATE_ON(BT656);
CLK_GATE_ON(BT656_2);
CLK_GATE_ON(PDM);
/* close AIU */
CLK_GATE_ON(AIU_IEC958);
CLK_GATE_ON(AIU_ICE958_AMCLK);
CLK_GATE_ON(AIU_AMCLK_MEASURE);
CLK_GATE_ON(AIU_AIFIFO2);
CLK_GATE_ON(AIU_MIXER_REG);
CLK_GATE_ON(AIU_ADC);
CLK_GATE_ON(AIU_TOP_LEVEL);
CLK_GATE_ON(AIU_AOCLK);
CLK_GATE_ON(AIU_AI_TOP_GLUE);
CLK_GATE_ON(AIU_I2S_OUT);
CLK_GATE_ON(ENC480P);
CLK_GATE_ON(DEMUX);
CLK_GATE_ON(EFUSE);
CLK_GATE_ON(BLK_MOV);
}
