.mux = { .shift = 12, .width = 2, .variable_prediv = { .index = 3, .shift = 6, .width = 2, }, }, .common = { .reg = 0x054, .features = CCU_FEATURE_VARIABLE_PREDIV, .hw.init = CLK_HW_INIT_PARENTS("ahb1", ahb1_parents, &ccu_div_ops, 0), }, }; static struct clk_div_table apb1_div_table[] = { { .val = 0, .div = 2 }, { .val = 1, .div = 2 }, { .val = 2, .div = 4 }, { .val = 3, .div = 8 }, { /* Sentinel */ }, }; static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, apb1_div_table, 0);
"pll-core" , "pll-periph" }; static const struct ccu_mux_fixed_prediv cpu_predivs[] = { { .index = 3, .div = 3, }, }; static struct ccu_mux cpu_clk = { .mux = { .shift = 16, .width = 2, .fixed_predivs = cpu_predivs, .n_predivs = ARRAY_SIZE(cpu_predivs), }, .common = { .reg = 0x054, .features = CCU_FEATURE_FIXED_PREDIV, .hw.init = CLK_HW_INIT_PARENTS("cpu", cpu_parents, &ccu_mux_ops, CLK_IS_CRITICAL), } }; static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0); static const char * const ahb_parents[] = { "axi" , "cpu", "pll-periph" }; static const struct ccu_mux_fixed_prediv ahb_predivs[] = { { .index = 2, .div = 2, }, }; static struct ccu_div ahb_clk = { .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), .mux = { .shift = 6, .width = 2,
static struct ccu_div ahb1_clk = { .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), .mux = { .shift = 12, .width = 2, .var_predivs = ahb1_predivs, .n_var_predivs = ARRAY_SIZE(ahb1_predivs), }, .common = { .reg = 0x054, .features = CCU_FEATURE_VARIABLE_PREDIV, .hw.init = CLK_HW_INIT_PARENTS("ahb1", ahb1_parents, &ccu_div_ops, 0), }, }; static struct clk_div_table apb1_div_table[] = { { .val = 0, .div = 2 }, { .val = 1, .div = 2 }, { .val = 2, .div = 4 }, { .val = 3, .div = 8 }, { /* Sentinel */ }, }; static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, apb1_div_table, 0); static const char * const apb2_parents[] = { "osc32k", "osc24M",
0x058, 0, 3, axi_div_table, 0); static const char * const gtbus_parents[] = { "osc24M", "pll-periph0", "pll-periph1", "pll-periph1" }; static SUNXI_CCU_M_WITH_MUX(gtbus_clk, "gtbus", gtbus_parents, 0x05c, 0, 2, 24, 2, CLK_IS_CRITICAL); static const char * const ahb_parents[] = { "gtbus", "pll-periph0", "pll-periph1", "pll-periph1" }; static struct ccu_div ahb0_clk = { .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), .mux = _SUNXI_CCU_MUX(24, 2), .common = { .reg = 0x060, .hw.init = CLK_HW_INIT_PARENTS("ahb0", ahb_parents, &ccu_div_ops, 0), }, }; static struct ccu_div ahb1_clk = { .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), .mux = _SUNXI_CCU_MUX(24, 2), .common = { .reg = 0x064, .hw.init = CLK_HW_INIT_PARENTS("ahb1", ahb_parents, &ccu_div_ops, 0), }, };
{ .index = 2, .shift = 6, .width = 2 }, { .index = 3, .shift = 6, .width = 2 }, }; static struct ccu_div ahb1_clk = { .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), .mux = { .shift = 12, .width = 2, .var_predivs = ahb1_predivs, .n_var_predivs = ARRAY_SIZE(ahb1_predivs), }, .common = { .reg = 0x054, .hw.init = CLK_HW_INIT_PARENTS("ahb1", ahb1_parents, &ccu_div_ops, 0), }, }; static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0); static const char * const apb2_parents[] = { "osc16M-d512", "osc24M", "pll-periph", "pll-periph" }; static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 0, 5, /* M */ 16, 2, /* P */ 24, 2, /* mux */ 0);
static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2", 0x79c, BIT(0), 0); static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0); static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0); static const char * const dram_parents[] = { "pll-ddr0" }; static struct ccu_div dram_clk = { .div = _SUNXI_CCU_DIV(0, 2), .mux = _SUNXI_CCU_MUX(24, 2), .common = { .reg = 0x800, .hw.init = CLK_HW_INIT_PARENTS("dram", dram_parents, &ccu_div_ops, CLK_IS_CRITICAL), }, }; static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus", 0x804, BIT(0), 0); static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus", 0x804, BIT(1), 0); static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus", 0x804, BIT(2), 0); static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus", 0x804, BIT(3), 0); static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus", 0x804, BIT(5), 0); static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
.mux = { .shift = 12, .width = 2, .variable_prediv = { .index = 3, .shift = 6, .width = 2, }, }, .common = { .reg = 0x054, .features = CCU_FEATURE_VARIABLE_PREDIV, .hw.init = CLK_HW_INIT_PARENTS("ahb1", ahb1_parents, &ccu_div_ops, 0), }, }; static struct clk_div_table apb1_div_table[] = { { .val = 0, .div = 2 }, { .val = 1, .div = 2 }, { .val = 2, .div = 4 }, { .val = 3, .div = 8 }, { /* Sentinel */ }, }; static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, apb1_div_table, 0); static const char * const apb2_parents[] = { "osc32k", "osc24M",