char Init_USART (USART_TypeDef* USART, unsigned int Baud_Rate, char Parity, char Bit_Stop, char data_length) { unsigned int CLK_USART=0x0, DIV_MANTISSA=0x0, DIV_FRACTION_I=0x0; float USARTDIV=0x0, DIV_FRACTION_F=0x0; // Erreur si parametres de la liaison incoherents if (((Parity==EVEN)||(Parity==ODD)||(Parity==DISABLED)) && ((Bit_Stop==STOP_BIT_MODE1)||(Bit_Stop==STOP_BIT_MODE2)||(Bit_Stop==STOP_BIT_MODE3)||(Bit_Stop==STOP_BIT_MODE4)) && ((data_length==WORD_LENGTH_8BITS)||(data_length==WORD_LENGTH_9BITS))) { // Activation de l'horloge pour les USARTs if (USART == USART1) RCC->APB2ENR |= RCC_APB2ENR_USART1EN; if (USART == USART2) RCC->APB1ENR |= RCC_APB1ENR_USART2EN; // Demarre USART USART->CR1 |= (1<<13); // Configuration de la taille de la donnee USART->CR1 |= (data_length<<12); // Configuration du bit STOP USART->CR2 |= (Bit_Stop<<12); // Configuration de la parite if (Parity == DISABLED) { USART->CR1 &= ~USART_CR1_PCE; } else { USART->CR1 |= USART_CR1_PCE; if (Parity == EVEN) USART->CR1 &= ~ USART_CR1_PS; else USART->CR1 |= USART_CR1_PS; } // Configuration de la vitesse de transmission // USART_DIV = CLK_USART / 16*BAUD_Rate // Mantisse a partir du bit 4 // Fraction a partir du bit 0 // Recuperation de l'Horloge if (USART == USART1) CLK_USART = CLOCK_GetPCLK2(); else CLK_USART = CLOCK_GetPCLK1(); // Calcul de l'USARTDIV USARTDIV = (float) CLK_USART / (float) (16*Baud_Rate); // Calcul de la mantisse et de la fraction pour le registre BR DIV_MANTISSA = USARTDIV; DIV_FRACTION_F = USARTDIV - DIV_MANTISSA; DIV_FRACTION_I = 16*DIV_FRACTION_F; // Si Overflow sur la fraction +1 sur la Mantisse if (DIV_FRACTION_I > 15) { DIV_FRACTION_I = 0; DIV_MANTISSA = DIV_MANTISSA + 1; } // On regle la vitesse de transmission dans le registre BR USART->BRR = (DIV_MANTISSA<<4) | (DIV_FRACTION_I<<0); // Pas d'erreur return 0; } else { // Erreur return 1; } }
//Initialisation de l'USART en transmission void Init_Transm_USART (USART_TypeDef *USART, int Baud) { // On definit les variables qui vont servir au calcul float Usart_DIV=0; unsigned int USARTDIV_Mantisse=0; u32 frequence_PCLK=0; // Activation des horloges de peripheriques USART if (USART == USART1) { (RCC->APB2ENR)=(RCC->APB2ENR) | RCC_APB2ENR_USART1EN; // Configuration de USART1_TX (broche PA9) Port_IO_Init_Alternative_Output(GPIOA,9); // Lecture de la frequence de PCLK2 frequence_PCLK = CLOCK_GetPCLK2(); } if (USART == USART2) { (RCC->APB1ENR)=(RCC->APB1ENR) | RCC_APB1ENR_USART2EN; // Configuration de USART2_TX (broche PA2) Port_IO_Init_Alternative_Output(GPIOA,2); // Lecture de la frequence de PCLK2 frequence_PCLK = CLOCK_GetPCLK1(); } if (USART == USART3) { (RCC->APB1ENR)=(RCC->APB1ENR) | RCC_APB1ENR_USART3EN; // Configuration de USART2_TX (broche PB10) Port_IO_Init_Alternative_Output(GPIOB,10); // Lecture de la frequence de PCLK2 frequence_PCLK = CLOCK_GetPCLK1(); } // Enable the USART by writing the UE bit in USART_CR1 register to 1 (bit 13) USART->CR1 |= (1 << 13); // Program the M bit in USART_CR1 to define the word length= 8 bits (bit 12); USART->CR1 &= ~(1 << 12); // Program the number of stop bits in USART_CR2 (bit 13:12) // 00 = 1 stop; 10 = 2 stops USART->CR2 &= ~(3 << 12); // Select baut rate USART_BRR register // horloge PCLK2 pour USART1 (72 MHz max) // horloge PCLK1 pour USART2,3,4 (36 MHz max) // Lecture de USART_DIV Usart_DIV = (float) frequence_PCLK/(16*Baud); // Recuperation de la Mantisse USARTDIV_Mantisse = (int) Usart_DIV; // Ecriture de la mantisse dans le registre BRR bits [4:15] USART->BRR = (USARTDIV_Mantisse << 4); // Calcul de la fraction dans la meme variable Usart_DIV = Usart_DIV - (float)USARTDIV_Mantisse; Usart_DIV *= 16; // Ecriture de la fraction dans le registre BRR USART->BRR |= ((u8)Usart_DIV); // Clear TC bit (transmission non fini) USART->SR &= ~(1 << 6); }