static void cn23xx_disable_vf_interrupt(struct octeon_device *oct, u8 intr_flag) { u32 q_no; if (intr_flag & OCTEON_OUTPUT_INTR) { for (q_no = 0; q_no < oct->num_oqs; q_no++) { /* Write all 1's in INT_LEVEL reg to disable PO_INT */ octeon_write_csr64( oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), 0x3fffffffffffff); } } if (intr_flag & OCTEON_INPUT_INTR) { for (q_no = 0; q_no < oct->num_oqs; q_no++) { octeon_write_csr64( oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no), (octeon_read_csr64( oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) & ~(CN23XX_INTR_CINT_ENB | CN23XX_PKT_IN_DONE_CNT_MASK))); } } if (intr_flag & OCTEON_MBOX_INTR) { octeon_write_csr64( oct, CN23XX_VF_SLI_PKT_MBOX_INT(0), (octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) & ~CN23XX_INTR_MBOX_ENB)); } }
static void cn23xx_enable_vf_interrupt(struct octeon_device *oct, u8 intr_flag) { struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip; u32 q_no, time_threshold; if (intr_flag & OCTEON_OUTPUT_INTR) { for (q_no = 0; q_no < oct->num_oqs; q_no++) { /* Set up interrupt packet and time thresholds * for all the OQs */ time_threshold = cn23xx_vf_get_oq_ticks( oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf)); octeon_write_csr64( oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), (CFG_GET_OQ_INTR_PKT(cn23xx->conf) | ((u64)time_threshold << 32))); } } if (intr_flag & OCTEON_INPUT_INTR) { for (q_no = 0; q_no < oct->num_oqs; q_no++) { /* Set CINT_ENB to enable IQ interrupt */ octeon_write_csr64( oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no), ((octeon_read_csr64( oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) & ~CN23XX_PKT_IN_DONE_CNT_MASK) | CN23XX_INTR_CINT_ENB)); } } /* Set queue-0 MBOX_ENB to enable VF mailbox interrupt */ if (intr_flag & OCTEON_MBOX_INTR) { octeon_write_csr64( oct, CN23XX_VF_SLI_PKT_MBOX_INT(0), (octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) | CN23XX_INTR_MBOX_ENB)); } }
static int cn23xx_vf_setup_mbox(struct lio_device *lio_dev) { struct lio_mbox *mbox; PMD_INIT_FUNC_TRACE(); if (lio_dev->mbox == NULL) { lio_dev->mbox = rte_zmalloc(NULL, sizeof(void *), 0); if (lio_dev->mbox == NULL) return -ENOMEM; } mbox = rte_zmalloc(NULL, sizeof(struct lio_mbox), 0); if (mbox == NULL) { rte_free(lio_dev->mbox); lio_dev->mbox = NULL; return -ENOMEM; } rte_spinlock_init(&mbox->lock); mbox->lio_dev = lio_dev; mbox->q_no = 0; mbox->state = LIO_MBOX_STATE_IDLE; /* VF mbox interrupt reg */ mbox->mbox_int_reg = (uint8_t *)lio_dev->hw_addr + CN23XX_VF_SLI_PKT_MBOX_INT(0); /* VF reads from SIG0 reg */ mbox->mbox_read_reg = (uint8_t *)lio_dev->hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0); /* VF writes into SIG1 reg */ mbox->mbox_write_reg = (uint8_t *)lio_dev->hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1); lio_dev->mbox[0] = mbox; rte_write64(LIO_PFVFSIG, mbox->mbox_read_reg); return 0; }
static int cn23xx_setup_vf_mbox(struct octeon_device *oct) { struct octeon_mbox *mbox = NULL; mbox = vmalloc(sizeof(*mbox)); if (!mbox) return 1; memset(mbox, 0, sizeof(struct octeon_mbox)); spin_lock_init(&mbox->lock); mbox->oct_dev = oct; mbox->q_no = 0; mbox->state = OCTEON_MBOX_STATE_IDLE; /* VF mbox interrupt reg */ mbox->mbox_int_reg = (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_PKT_MBOX_INT(0); /* VF reads from SIG0 reg */ mbox->mbox_read_reg = (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0); /* VF writes into SIG1 reg */ mbox->mbox_write_reg = (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1); INIT_DELAYED_WORK(&mbox->mbox_poll_wk.work, cn23xx_vf_mbox_thread); mbox->mbox_poll_wk.ctxptr = mbox; oct->mbox[0] = mbox; writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); return 0; }