/* Handle a break interrupt. */ void frv_break_interrupt ( SIM_CPU *current_cpu, struct frv_interrupt *interrupt, IADDR current_pc ) { IADDR new_pc; /* BPCSR=PC BPSR.BS=PSR.S BPSR.BET=PSR.ET PSR.S=1 PSR.ET=0 TBR.TT=0xff PC=TBR */ /* Must set PSR.S first to allow access to supervisor-only spr registers. */ SET_H_BPSR_BS (GET_H_PSR_S ()); SET_H_BPSR_BET (GET_H_PSR_ET ()); SET_H_PSR_S (1); SET_H_PSR_ET (0); /* Must set PSR.S first to allow access to supervisor-only spr registers. */ SET_H_SPR (H_SPR_BPCSR, current_pc); /* Set the new PC in the TBR. */ SET_H_TBR_TT (interrupt->handler_offset); new_pc = GET_H_SPR (H_SPR_TBR); SET_H_PC (new_pc); CPU_DEBUG_STATE (current_cpu) = 1; }
/* Return from trap. */ USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field) { USI new_pc; /* if (normal running mode and debug_field==0 PC=PCSR PSR.ET=1 PSR.S=PSR.PS else if (debug running mode and debug_field==1) PC=(BPCSR) PSR.ET=BPSR.BET PSR.S=BPSR.BS change to normal running mode */ int psr_s = GET_H_PSR_S (); int psr_et = GET_H_PSR_ET (); /* Check for exceptions in the priority order listed in the FRV Architecture Volume 2. */ if (! psr_s) { /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */ if (! psr_et) { SIM_DESC sd = CPU_STATE (current_cpu); sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); } /* privileged_instruction interrupt will have already been queued by frv_detect_insn_access_interrupts. */ new_pc = pc + 4; } else if (psr_et) { /* Halt if PSR.S is set. See chapter 6 of the LSI. */ if (psr_s) { SIM_DESC sd = CPU_STATE (current_cpu); sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); } frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); new_pc = pc + 4; } else if (! CPU_DEBUG_STATE (current_cpu) && debug_field == 0) { USI psr = GET_PSR (); /* Return from normal running state. */ new_pc = GET_H_SPR (H_SPR_PCSR); SET_PSR_ET (psr, 1); SET_PSR_S (psr, GET_PSR_PS (psr)); sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); } else if (CPU_DEBUG_STATE (current_cpu) && debug_field == 1) { USI psr = GET_PSR (); /* Return from debug state. */ new_pc = GET_H_SPR (H_SPR_BPCSR); SET_PSR_ET (psr, GET_H_BPSR_BET ()); SET_PSR_S (psr, GET_H_BPSR_BS ()); sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); CPU_DEBUG_STATE (current_cpu) = 0; } else new_pc = pc + 4; return new_pc; }