void BootEntryLoader()
{
struct CompressedImage_Header* hdr = &PortBooterLoader_Dat;
void* data = &hdr[1];
LZ77_Decompress( (UINT8*)data, hdr->Compressed, (UINT8*)hdr->Destination, hdr->Uncompressed );
CPU_FlushCaches();
((void(*)())hdr->Destination)();
}
void BootEntryLoader()
{
struct CompressedImage_Header* hdr = &TinyBooterCompressed_Dat;
void* data = &hdr[ 1 ];
APP_ENTRY_POINT AppEntry = (APP_ENTRY_POINT)hdr->Destination;
LZ77_Decompress( (UINT8*)data, hdr->Compressed, (UINT8*)hdr->Destination, hdr->Uncompressed );
CPU_FlushCaches();
AppEntry();
}
I28F_16_BS_Driver::CHIP_WORD __section("SectionForFlashOperations") I28F_16_BS_Driver::Action_EraseSector( void* context, volatile CHIP_WORD * Sector, MEMORY_MAPPED_NOR_BLOCK_CONFIG* FlashConfig )
{
NATIVE_PROFILE_HAL_DRIVERS_FLASH();
CHIP_WORD StatusRegister;
///////////////////////////////////
//
//
FLASH_BEGIN_PROGRAMMING_FAST( );
Sector = (volatile CHIP_WORD*)CPU_GetUncachableAddress( Sector );
// now setup erasing
*Sector = BLOCK_ERASE_SETUP;
*Sector = BLOCK_ERASE_CONFIRM;
// wait for device to signal completion
// break when the device signals completion by looking for Data (0xff erasure value) on I/O 7 (a 0 on I/O 7 indicates erasure in progress)
while((*Sector & SR_WSM_READY) != SR_WSM_READY);
StatusRegister = *Sector;
// error conditions must be cleared
*Sector = CLEAR_STATUS_REGISTER;
*Sector = ENTER_READ_ARRAY_MODE;
CPU_FlushCaches();
FLASH_END_PROGRAMMING_FAST( "I28F_16 EraseSector", Sector );
//
//
///////////////////////////////////
return StatusRegister;
}
void BootstrapCode_MMU()
{
// Fill Translation table with faults.
ARM9_MMU::InitializeL1(c_Bootstrap_BaseOfTTBs);
// Direct map for the APB registers (0xFFF00000 ~ 0xFFFFFFFF)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
c_Bootstrap_Register_Begin, // mapped address
c_Bootstrap_Register_Begin, // physical address
c_Bootstrap_Register_End - c_Bootstrap_Register_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
FALSE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Direct map SDRAM (cachable)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
c_Bootstrap_SDRAM_Begin, // mapped address
c_Bootstrap_SDRAM_Begin, // physical address
c_Bootstrap_SDRAM_End - c_Bootstrap_SDRAM_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
TRUE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Remap SRAM @0x000000000 (cachable)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
0x00000000, // mapped address
c_Bootstrap_SRAM_Begin, // physical address
c_Bootstrap_SRAM_End - c_Bootstrap_SRAM_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
TRUE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Direct map SRAM (cachable)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
c_Bootstrap_SRAM_Begin, // mapped address
c_Bootstrap_SRAM_Begin, // physical address
c_Bootstrap_SRAM_End - c_Bootstrap_SRAM_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
TRUE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Direct map for the LCD registers(0x00600000~0x006FFFFF)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
AT91C_BASE_LCDC, // mapped address
AT91C_BASE_LCDC, // physical address
ARM9_MMU::c_MMU_L1_size, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
FALSE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Direct map for the FLASH (uncachable)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
c_Bootstrap_FLASH_Begin, // mapped address
c_Bootstrap_FLASH_Begin, // physical address
c_Bootstrap_FLASH_End - c_Bootstrap_FLASH_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
FALSE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
#ifdef PLATFORM_ARM_SAM9RL64_ANY
// Direct map for the USBHS buffer registers(0x00600000~0x006FFFFF)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
AT91C_BASE_UDP_DMA, // mapped address
AT91C_BASE_UDP_DMA, // physical address
ARM9_MMU::c_MMU_L1_size, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
FALSE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
#endif
// TODO: UNCOMMENT if FLASH is added on external bus
//
// Direct map for the FLASH (cachable)
// ARM9_MMU::GenerateL1_Sections(
// c_Bootstrap_BaseOfTTBs, // base of TTBs
// c_Bootstrap_FLASH_Begin, // mapped address
// c_Bootstrap_FLASH_Begin, // physical address
// c_Bootstrap_FLASH_End - c_Bootstrap_FLASH_Begin, // length to be mapped
// ARM9_MMU::c_AP__Manager, // AP
// 0, // Domain
// TRUE, // Cacheable
// FALSE, // Buffered
// FALSE); // Extended
// Direct map for the FLASH (uncachable)
// ARM9_MMU::GenerateL1_Sections(
// c_Bootstrap_BaseOfTTBs, // base of TTBs
// CPU_GetUncachableAddress(c_Bootstrap_FLASH_Begin), // mapped address
// c_Bootstrap_FLASH_Begin, // physical address
// c_Bootstrap_FLASH_End - c_Bootstrap_FLASH_Begin, // length to be mapped
// ARM9_MMU::c_AP__Manager, // AP
// 0, // Domain
// FALSE, // Cacheable
// FALSE, // Buffered
// FALSE); // Extended
//
CPU_FlushCaches();
CPU_EnableMMU( c_Bootstrap_BaseOfTTBs );
}
BOOL SD_BS_Driver::WriteX(void *context, ByteAddress phyAddr, UINT32 NumBytes, BYTE *pSectorBuff, BOOL ReadModifyWrite, BOOL fIncrementDataPtr )
{
NATIVE_PROFILE_PAL_FLASH();
__IO SD_Error errorstatus = SD_OK;
UINT32 RangeIndex;
UINT32 RegionIndex;
UINT32 BytesPerSector;
UINT32 offset;
UINT32 bytes;
BYTE response;
BLOCK_CONFIG* pConfig = (BLOCK_CONFIG*)context;
CHIP_WORD *pData, *pWrite;
// find the corresponding region
if(!pConfig->BlockDeviceInformation->FindRegionFromAddress(phyAddr, RegionIndex, RangeIndex))
return FALSE;
ByteAddress StartSector = pConfig->BlockDeviceInformation->PhysicalToSectorAddress( &pConfig->BlockDeviceInformation->Regions[RegionIndex], phyAddr);
pData = (CHIP_WORD*)pSectorBuff;
BytesPerSector = pConfig->BlockDeviceInformation->BytesPerSector;
offset = phyAddr - (StartSector * BytesPerSector);
bytes = (NumBytes + offset > BytesPerSector ? BytesPerSector - offset : NumBytes);
while(NumBytes > 0)
{
// if we are using memset, or if the bytes written are less than the BytesPerSector then do read/modify/write
if(!fIncrementDataPtr || (bytes != BytesPerSector))
{
if(bytes != BytesPerSector)
{
if(!ReadSector(StartSector, 0, BytesPerSector, s_sectorBuff, BytesPerSector))
{
return FALSE;
}
}
pWrite = (CHIP_WORD*)&s_sectorBuff[0];
if(fIncrementDataPtr)
{
memcpy(&pWrite[offset], pData, bytes);
}
else
{
memset(&pWrite[offset], *pData, bytes);
}
}
else
{
pWrite = pData;
}
CPU_FlushCaches();
errorstatus = SD_WriteBlock(pWrite, (StartSector * BytesPerSector), BytesPerSector);
while(SD_GetStatus() != SD_TRANSFER_OK);
if(fIncrementDataPtr) pData = (CHIP_WORD*)((UINT32)pData + bytes);
NumBytes -= bytes;
offset = 0;
StartSector++;
bytes = __min(BytesPerSector, NumBytes);
}
if(errorstatus == SD_OK)
return TRUE;
else
return FALSE;
}
