BOOL AD7466_Driver::Initialize()
{
AD7466_CONFIG* Config = &g_AD7466_Config;
HAL_CONFIG_BLOCK::ApplyConfig( Config->GetDriverName(), Config, sizeof(*Config) );
g_AD7466_Driver.m_Rb = Config->Thermistor_Rb; // 3.24k nominally, but may change for earlier P3s to 32.4k
VoltageFilter_Reset();
// General Rule: Enable all GPIO OUTPUTs to peripherals before checking inputs from it
// enable the CS for the ADC and bring it high (inactive)
CPU_GPIO_EnableOutputPin( Config->SPI_Config.DeviceCS, !Config->SPI_Config.CS_Active );
// enable the ADMUX GPIO output control lines, and leave it inactive
CPU_GPIO_EnableOutputPin( Config->ADMUX_EN_L_GPIO_PIN, TRUE );
CPU_GPIO_EnableOutputPin( Config->ADMUX_A0_GPIO_PIN, FALSE );
CPU_GPIO_EnableOutputPin( Config->ADMUX_A1_GPIO_PIN, FALSE );
// read the battery temp, at init, to:
// 1. clear the over temp state set as default
// 2. decide which bottom resistor we have
INT32 DegreesCelcius_x10;
if(!Temperature( DegreesCelcius_x10 ))
{
ASSERT(0);
return FALSE;
}
return TRUE;
}
void LPC24XX_USART_Driver::ProtectPins ( int ComPortNum, BOOL On )
{
ASSERT(LPC24XX_USART_Driver::IsValidPortNum(ComPortNum));
static BOOL COM1_PinsProtected = TRUE; // start out doing work on first unprotect
static BOOL COM2_PinsProtected = TRUE; // start out doing work on first unprotect
static BOOL COM3_PinsProtected = TRUE; // start out doing work on first unprotect
static BOOL COM4_PinsProtected = TRUE; // start out doing work on first unprotect
GLOBAL_LOCK(irq);
UINT32 SER_TXD;
UINT32 SER_RXD;
BOOL* PinsProtected;
switch(ComPortNum)
{
case c_COM1: SER_TXD = LPC24XX_USART::c_SER1_TXD; SER_RXD = LPC24XX_USART::c_SER1_RXD; PinsProtected = &COM1_PinsProtected; break;
case c_COM2: SER_TXD = LPC24XX_USART::c_SER2_TXD; SER_RXD = LPC24XX_USART::c_SER2_RXD; PinsProtected = &COM2_PinsProtected; break;
case c_COM3: SER_TXD = LPC24XX_USART::c_SER3_TXD; SER_RXD = LPC24XX_USART::c_SER3_RXD; PinsProtected = &COM3_PinsProtected; break;
case c_COM4: SER_TXD = LPC24XX_USART::c_SER4_TXD; SER_RXD = LPC24XX_USART::c_SER4_RXD; PinsProtected = &COM4_PinsProtected; break;
default: return;
}
if (On)
{
if(!*PinsProtected)
{
*PinsProtected = TRUE;
TxBufferEmptyInterruptEnable( ComPortNum, FALSE );
// TODO Add config for uart pin protected state
CPU_GPIO_EnableOutputPin( SER_TXD, RESISTOR_DISABLED );
RxBufferFullInterruptEnable( ComPortNum, FALSE );
// TODO Add config for uart pin protected state
CPU_GPIO_EnableOutputPin( SER_RXD, RESISTOR_DISABLED );
}
}
else
{
if(*PinsProtected)
{
*PinsProtected = FALSE;
// Connect pin to UART
CPU_GPIO_DisablePin( SER_TXD, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
// Connect pin to UART
CPU_GPIO_DisablePin( SER_RXD, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
TxBufferEmptyInterruptEnable( ComPortNum, TRUE );
RxBufferFullInterruptEnable( ComPortNum, TRUE );
}
}
}
void __section("SectionForBootstrapOperations") BootstrapCode_GPIO()
{
// Enable GPIO clocks for ports A - E
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN;
// TODO: Restore at the end of bootloader?
CPU_GPIO_EnableOutputPin(LED3, FALSE);
CPU_GPIO_EnableOutputPin(LED4, FALSE);
CPU_GPIO_EnableOutputPin(LED5, FALSE);
CPU_GPIO_EnableOutputPin(LED6, FALSE);
}
void __section(SectionForBootstrapOperations) BootstrapCode_GPIO() {
/* Enable GPIO clocks */
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN
| RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN;
CPU_GPIO_EnableOutputPin(3 * 16 + 12, FALSE); // PD12 = LED1
CPU_GPIO_EnableOutputPin(3 * 16 + 13, FALSE); // PD13 = LED2
CPU_GPIO_EnableOutputPin(3 * 16 + 14, FALSE); // PD14 = LED3
CPU_GPIO_EnableOutputPin(3 * 16 + 15, FALSE); // PD15 = LED4
}
void __section(SectionForBootstrapOperations) BootstrapCode_GPIO() {
/* Enable GPIO clocks */
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN
| RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN;
CPU_GPIO_EnableOutputPin(6 * 16 + 6, FALSE); // PG6 = LED1
CPU_GPIO_EnableOutputPin(6 * 16 + 8, FALSE); // PG8 = LED2
CPU_GPIO_EnableOutputPin(8 * 16 + 9, FALSE); // PI9 = LED3
CPU_GPIO_EnableOutputPin(2 * 16 + 7, FALSE); // PC7 = LED4
//STM3210E_InitSRam(); // initialize FSMC
}
BOOL CPU_SPI_Xaction_Start(const SPI_CONFIGURATION& Configuration)
{
if (Configuration.SPI_mod >= TOTAL_SPI_PORT) return FALSE;
LPC_SSP_T *spi = SPI_REG(Configuration.SPI_mod);
int Bits, Mode;
// Configure options and clock
Bits = (Configuration.MD_16bits) ? 16 : 8;
Mode = (Configuration.MSK_IDLE) ? 2 : 0; // ToDo: Check
Mode |= (!Configuration.MSK_SampleEdge) ? 1 : 0;
SPI_Config(spi, Bits, Mode, 0);
SPI_Frequency(spi, (1000 * Configuration.Clock_RateKHz));
// I/O setup
GPIO_PIN msk, miso, mosi;
CPU_SPI_GetPins(Configuration.SPI_mod, msk, miso, mosi);
UINT32 alternate = 0x252; // AF5 = SPI1/SPI2
if (Configuration.SPI_mod == 2) alternate = 0x262; // AF6 = SPI3, speed = 2 (50MHz)
CPU_GPIO_DisablePin(msk, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(miso, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(mosi, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
// CS setup
CPU_GPIO_EnableOutputPin(Configuration.DeviceCS, Configuration.CS_Active);
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled(Configuration.CS_Setup_uSecs);
}
return TRUE;
}
int AT91_EMAC_LWIP_Driver::Open(int index)
{
/* Network interface variables */
struct ip_addr ipaddr, subnetmask, gateway;
struct netif *pNetIF;
int len;
const SOCK_NetworkConfiguration *iface;
/* Apply network configuration */
iface = &g_NetworkConfig.NetworkInterfaces[index];
len = g_AT91_EMAC_NetIF.hwaddr_len;
if(len == 0 || iface->macAddressLen < len)
{
len = iface->macAddressLen;
g_AT91_EMAC_NetIF.hwaddr_len = len;
}
memcpy(g_AT91_EMAC_NetIF.hwaddr, iface->macAddressBuffer, len);
if(0 == (iface->flags & SOCK_NETWORKCONFIGURATION_FLAGS_DHCP))
{
ipaddr.addr = iface->ipaddr;
gateway.addr = iface->gateway;
subnetmask.addr = iface->subnetmask;
}
else
{
/* Set network address variables - this will be set by either DHCP or when the configuration is applied */
IP4_ADDR(&gateway, 0,0,0,0);
IP4_ADDR(&ipaddr, 0,0,0,0);
IP4_ADDR(&subnetmask, 255,255,255,0);
}
// PHY Power Up
CPU_GPIO_EnableOutputPin(g_AT91_EMAC_LWIP_Config.PHY_PD_GPIO_Pin, FALSE);
// Enable Interrupt
CPU_INTC_ActivateInterrupt(AT91C_ID_EMAC, (HAL_CALLBACK_FPN)AT91_EMAC_LWIP_interrupt, &g_AT91_EMAC_NetIF);
g_AT91_EMAC_NetIF.flags = NETIF_FLAG_IGMP | NETIF_FLAG_BROADCAST;
pNetIF = netif_add( &g_AT91_EMAC_NetIF, &ipaddr, &subnetmask, &gateway, NULL, AT91_EMAC_ethhw_init, ethernet_input );
netif_set_default( pNetIF );
LWIP_STATUS_setorclear( LWIP_STATUS_LinkUp, 0 != dm9161_lwip_GetLinkStatus( ) );
if (LWIP_STATUS_isset(LWIP_STATUS_LinkUp))
{
netif_set_link_up( pNetIF );
netif_set_up ( pNetIF );
Network_PostEvent( NETWORK_EVENT_TYPE__AVAILABILITY_CHANGED, NETWORK_EVENT_FLAGS_IS_AVAILABLE );
}
/* Initialize the continuation routine for the driver interrupt and receive */
InitContinuations( pNetIF );
return g_AT91_EMAC_NetIF.num;
}
BOOL CPU_SPI_Xaction_Start( const SPI_CONFIGURATION& Configuration )
{
NATIVE_PROFILE_HAL_PROCESSOR_SPI();
if (Configuration.SPI_mod >= STM32F4_SPI_MODS) return FALSE;
// CS setup
CPU_GPIO_EnableOutputPin( Configuration.DeviceCS, Configuration.CS_Active );
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Setup_uSecs );
}
// I/O setup
GPIO_PIN msk, miso, mosi;
CPU_SPI_GetPins(Configuration.SPI_mod, msk, miso, mosi);
UINT32 alternate = 0x252; // AF5 = SPI1/SPI2
if (Configuration.SPI_mod == 2) alternate = 0x262; // AF6 = SPI3, speed = 2 (50MHz)
CPU_GPIO_DisablePin( msk, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin( miso, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin( mosi, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
switch (Configuration.SPI_mod) {
case 0: RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; break; // enable SPI1 clock
case 1: RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; break; // enable SPI2 clock
case 2: RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; break; // enable SPI3 clock
}
ptr_SPI_TypeDef spi = g_STM32_Spi_Port[Configuration.SPI_mod];
// set mode bits
UINT32 cr1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR | SPI_CR1_SPE;
if (Configuration.MD_16bits) cr1 |= SPI_CR1_DFF;
if (Configuration.MSK_IDLE) cr1 |= SPI_CR1_CPOL | SPI_CR1_CPHA;
if (!Configuration.MSK_SampleEdge) cr1 ^= SPI_CR1_CPHA; // toggle phase
// set clock prescaler
UINT32 clock = SYSTEM_APB2_CLOCK_HZ / 2000; // SPI1 on APB2
if (Configuration.SPI_mod != 0) clock = SYSTEM_APB1_CLOCK_HZ / 2000; // SPI2/3 on APB1
if (clock > Configuration.Clock_RateKHz << 3) {
clock >>= 4;
cr1 |= SPI_CR1_BR_2;
}
int AT91_EMAC_LWIP_Driver::Open(int index)
{
/* Network interface variables */
struct ip_addr ipaddr, subnetmask, gateway;
struct netif *pNetIF;
int len;
const SOCK_NetworkConfiguration *iface;
/* Apply network configuration */
iface = &g_NetworkConfig.NetworkInterfaces[index];
len = g_AT91_EMAC_NetIF.hwaddr_len;
if(len == 0 || iface->macAddressLen < len)
{
len = iface->macAddressLen;
g_AT91_EMAC_NetIF.hwaddr_len = len;
}
memcpy(g_AT91_EMAC_NetIF.hwaddr, iface->macAddressBuffer, len);
ipaddr.addr = iface->ipaddr;
gateway.addr = iface->gateway;
subnetmask.addr = iface->subnetmask;
// PHY Power Up
CPU_GPIO_EnableOutputPin(g_AT91_EMAC_LWIP_Config.PHY_PD_GPIO_Pin, FALSE);
// Enable Interrupt
CPU_INTC_ActivateInterrupt(AT91C_ID_EMAC, (HAL_CALLBACK_FPN)AT91_EMAC_LWIP_interrupt, &g_AT91_EMAC_NetIF);
/* Initialize the continuation routine for the driver interrupt and receive */
InitContinuations( pNetIF );
pNetIF = netif_add( &g_AT91_EMAC_NetIF, &ipaddr, &subnetmask, &gateway, NULL, AT91_EMAC_ethhw_init, ethernet_input );
netif_set_default( pNetIF );
LwipNetworkStatus = dm9161_lwip_GetLinkStatus( );
if (LwipNetworkStatus)
{
netif_set_up( pNetIF );
}
/* Initialize the continuation routine for the driver interrupt and receive */
InitContinuations( pNetIF );
return g_AT91_EMAC_NetIF.num;
}
void Piezo_Driver::Initialize()
{
HAL_CONFIG_BLOCK::ApplyConfig( g_pPIEZO_Config->GetDriverName(), g_pPIEZO_Config, sizeof(*g_pPIEZO_Config) );
g_Piezo_Driver.m_ToneToPlay .Initialize();
g_Piezo_Driver.m_ToneToRelease.Initialize();
g_Piezo_Driver.m_ToneDone .InitializeForISR ( ToneDone_ISR );
g_Piezo_Driver.m_ToneRelease.InitializeCallback( ToneRelease );
g_Piezo_Driver.m_TonePlaying = NULL;
// clear the hardware to proper disabled state
for(int i = 0; i < 2; i++)
{
PWM_CONFIG* PWM_Config = &g_pPIEZO_Config->PWM_Config[i];
if(PWM_Config->PWM_Output.Pin != GPIO_PIN_NONE)
{
CPU_GPIO_EnableOutputPin( PWM_Config->PWM_Output.Pin, PWM_Config->PWM_DisabledState );
}
}
}
BOOL LPC24XX_SPI_Driver::Xaction_Start( const SPI_CONFIGURATION& Configuration )
{
if(!g_LPC24XX_SPI_Driver.m_Enabled[Configuration.SPI_mod])
{
g_LPC24XX_SPI_Driver.m_Enabled[Configuration.SPI_mod] = TRUE;
UINT32 index = Configuration.SPI_mod;
LPC24XX_SPI & SPI = LPC24XX::SPI(index);
// first build the mode register
SPI.SPCR = LPC24XX_SPI::ConfigurationToMode( Configuration );
// Set SPI Clock
SPI.SPCCR = LPC24XX_SPI::c_SPI_Clk_KHz / (Configuration.Clock_RateKHz);
// first set CS active as soon as clock and data pins are in proper initial state
if(Configuration.DeviceCS != LPC24XX_GPIO::c_Pin_None)
{
CPU_GPIO_EnableOutputPin( Configuration.DeviceCS, Configuration.CS_Active );
}
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Setup_uSecs );
}
}
else
{
lcd_printf( "\fSPI Collision 3\r\n" );
HARD_BREAKPOINT();
return FALSE;
}
return TRUE;
}
int AT91_EMAC_Driver::Open()
{
int use_default_multicast;
memset(&g_AT91_EMAC_Driver.m_currentDhcpSession, 0, sizeof(g_AT91_EMAC_Driver.m_currentDhcpSession));
// PHY Power Up
CPU_GPIO_EnableOutputPin(g_AT91_EMAC_Config.PHY_PD_GPIO_Pin, FALSE);
/* Open the interface first */
g_AT91_EMAC_Driver.m_interfaceNumber = xn_interface_open_config(AT91EMAC_DEVICE,
0, /* minor_number */
0, /* ioaddress */
0, /* irq value */
0 /* mem_address) */
);
if (g_AT91_EMAC_Driver.m_interfaceNumber == -1)
{
return -1;
}
use_default_multicast = 1;
if (xn_interface_opt(g_AT91_EMAC_Driver.m_interfaceNumber,
IO_DEFAULT_MCAST,
(RTP_PFCCHAR)&use_default_multicast,
sizeof(int)) == -1)
{
/* Failed to set the default multicast interface */
debug_printf("EMAC: Failed to set the default multicast interface\r\n");
}
CPU_INTC_ActivateInterrupt(AT91C_ID_EMAC, AT91_EMAC_interrupt, NULL);
return g_AT91_EMAC_Driver.m_interfaceNumber;
}
BOOL MC9328MXL_SPI_Driver::Xaction_Stop( const SPI_CONFIGURATION& Configuration )
{
NATIVE_PROFILE_HAL_PROCESSOR_SPI();
if(g_MC9328MXL_SPI_Driver.m_Enabled[Configuration.SPI_mod])
{
UINT32 index = Configuration.SPI_mod;
MC9328MXL_SPI & SPI = MC9328MXL::SPI(index);
// we should have cleared the last TBF on the last RBF true setting
// we should never bring CS inactive with the shifter busy
ASSERT( SPI.TransmitBufferEmpty());
ASSERT( SPI.ReceiveBufferEmpty ());
ASSERT( SPI.ShiftBufferEmpty ());
if(Configuration.CS_Hold_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Hold_uSecs );
}
// avoid noise drawing excess power on a floating line by putting this in pulldown
#if defined(PLATFORM_ARM_MC9328MXS)
CPU_GPIO_EnableInputPin( MC9328MXL_SPI::c_SPI1_MISO, FALSE, NULL, GPIO_INT_NONE, RESISTOR_PULLUP );
#else
if (index == MC9328MXL_SPI::c_SPI1)
{
CPU_GPIO_EnableInputPin( MC9328MXL_SPI::c_SPI1_MISO, FALSE, NULL, GPIO_INT_NONE, RESISTOR_PULLUP );
}
else
{
CPU_GPIO_EnableInputPin( MC9328MXL_SPI::c_SPI2_MISO, FALSE, NULL, GPIO_INT_NONE, RESISTOR_PULLUP );
}
#endif
// next, bring the CS to the proper inactive state
if((Configuration.DeviceCS != MC9328MXL_GPIO::c_Pin_None) && (Configuration.DeviceCS != MC9328MXL_SPI::c_SPI1_SS))
{
CPU_GPIO_SetPinState( Configuration.DeviceCS, !Configuration.CS_Active );
}
// make sure that we don't trigger the SS pin for LCD on the iMXS board, this may change if Freescale change their circuitry
// can remove if not use on imxs platform
// be safe, as LCD SPI access will use this function as well, set it back to Output
#if (HARDWARE_BOARD_TYPE >= HARDWARE_BOARD_i_MXS_DEMO_REV_V1_2)
CPU_GPIO_EnableOutputPin( MC9328MXL_SPI::c_SPI1_SS, TRUE );
#endif
// put pins in output low state when not in use to avoid noise since clock stop and reset will cause these to become inputs
#if defined(PLATFORM_ARM_MC9328MXS)
CPU_GPIO_EnableOutputPin( MC9328MXL_SPI::c_SPI1_SCLK, FALSE );
CPU_GPIO_EnableOutputPin( MC9328MXL_SPI::c_SPI1_MOSI, FALSE );
#else
if (index == MC9328MXL_SPI::c_SPI1)
{
CPU_GPIO_EnableOutputPin( MC9328MXL_SPI::c_SPI1_SCLK, FALSE );
CPU_GPIO_EnableOutputPin( MC9328MXL_SPI::c_SPI1_MOSI, FALSE );
}
else
{
CPU_GPIO_EnableOutputPin( MC9328MXL_SPI::c_SPI2_SCLK, FALSE );
CPU_GPIO_EnableOutputPin( MC9328MXL_SPI::c_SPI2_MOSI, FALSE );
}
#endif
// off SPI module
SPI.CONTROLREG &= ~SPI.CONTROLREG_SPIEN;
g_MC9328MXL_SPI_Driver.m_Enabled[Configuration.SPI_mod] = FALSE;
}
else
{
lcd_printf("\fSPI Collision 4\r\n");
HARD_BREAKPOINT();
return FALSE;
}
return TRUE;
}
////////////////////////////////////////////////////////////////////////////////
// The TinyBooter_OnStateChange method is an event handler for state changes in
// the TinyBooter. It is designed to help porting kit users control the tinybooter
// execution and allow them to add diagnostics.
////////////////////////////////////////////////////////////////////////////////
void TinyBooter_OnStateChange( TinyBooterState state, void* data, void ** retData )
{
switch(state)
{
////////////////////////////////////////////////////////////////////////////////////
// State_EnterBooterMode - TinyBooter has entered upload mode
////////////////////////////////////////////////////////////////////////////////////
case State_EnterBooterMode:
CPU_GPIO_EnableOutputPin(LED1, TRUE);
CPU_GPIO_EnableOutputPin(LED2, TRUE);
CPU_GPIO_EnableOutputPin(LED3, TRUE);
#if defined(TARGETLOCATION_RAM)
CPU_GPIO_EnableOutputPin(LED4, TRUE);
#else
CPU_GPIO_EnableOutputPin(LED4, FALSE);
#endif
hal_fprintf( STREAM_LCD, "Waiting\r" );
break;
////////////////////////////////////////////////////////////////////////////////////
// State_ButtonPress - A button was pressed while Tinybooter
// The data parameter is a pointer to the timeout value for the booter mode.
////////////////////////////////////////////////////////////////////////////////////
case State_ButtonPress:
if(NULL != data)
{
UINT32 down, up;
INT32* timeout_ms = (INT32*)data;
// wait forever if a button was pressed
*timeout_ms = -1;
// process buttons
while(Buttons_GetNextStateChange(down, up))
{
// leave a way to exit boot mode incase it was accidentally entered
if(0 != (down & BUTTON_ENTR))
{
// force an enumerate and launch
*timeout_ms = 0;
}
}
}
break;
////////////////////////////////////////////////////////////////////////////////////
// State_ValidCommunication - TinyBooter has received valid communication from the host
// The data parameter is a pointer to the timeout value for the booter mode.
////////////////////////////////////////////////////////////////////////////////////
case State_ValidCommunication:
if(NULL != data)
{
INT32* timeout_ms = (INT32*)data;
// if we received any com/usb data then let's change the timeout to at least 20 seconds
if(*timeout_ms != -1 && *timeout_ms < 20000)
{
*timeout_ms = 20000;
}
}
break;
////////////////////////////////////////////////////////////////////////////////////
// State_Timeout - The default timeout for TinyBooter has expired and TinyBooter will
// perform an EnumerateAndLaunch
////////////////////////////////////////////////////////////////////////////////////
case State_Timeout:
break;
////////////////////////////////////////////////////////////////////////////////////
// State_MemoryXXX - Identifies memory accesses.
////////////////////////////////////////////////////////////////////////////////////
case State_MemoryWrite:
hal_fprintf( STREAM_LCD, "Wr: 0x%08x\r", (UINT32)data );
break;
case State_MemoryErase:
hal_fprintf( STREAM_LCD, "Er: 0x%08x\r", (UINT32)data );
break;
////////////////////////////////////////////////////////////////////////////////////
// State_CryptoXXX - Start and result of Crypto signature check
////////////////////////////////////////////////////////////////////////////////////
case State_CryptoStart:
hal_fprintf( STREAM_LCD, "Chk signature \r" );
hal_printf( "Chk signature \r" );
break;
// The data parameter is a boolean that represents signature PASS/FAILURE
case State_CryptoResult:
if((bool)data)
{
hal_fprintf( STREAM_LCD, "Signature PASS\r\n\r\n" );
hal_printf( "Signature PASS\r\n\r\n" );
}
else
{
hal_fprintf( STREAM_LCD, "Signature FAIL\r\n\r\n" );
hal_printf( "Signature FAIL\r\n\r\n" );
}
DebuggerPort_Flush(HalSystemConfig.DebugTextPort);
break;
////////////////////////////////////////////////////////////////////////////////////
// State_Launch - The host has requested to launch an application at a given address,
// or a timeout has occured and TinyBooter is about to launch the
// first application it finds in FLASH.
//
// The data parameter is a UINT32 value representing the launch address
////////////////////////////////////////////////////////////////////////////////////
case State_Launch:
if(NULL != data)
{
CPU_GPIO_EnableOutputPin(LED1, FALSE);
hal_fprintf( STREAM_LCD, "Starting application at 0x%08x\r\n", (UINT32)data );
// copy the native code from the Load area to execute area.
// set the *retAddres to real execute address after loading the data
// *retData = exeAddress
*retData =(void*) ((UINT32)data | 1); // set Thumb bit!
}
break;
}
}
BOOL MC9328MXL_SPI_Driver::Xaction_Start( const SPI_CONFIGURATION& Configuration )
{
NATIVE_PROFILE_HAL_PROCESSOR_SPI();
if(!g_MC9328MXL_SPI_Driver.m_Enabled[Configuration.SPI_mod])
{
g_MC9328MXL_SPI_Driver.m_Enabled[Configuration.SPI_mod] = TRUE;
UINT32 index = Configuration.SPI_mod;
MC9328MXL_SPI & SPI = MC9328MXL::SPI(index);
// make sure we didn't start one in the middle of an existing transaction
if( SPI.CONTROLREG & SPI.CONTROLREG_SPIEN )
{
lcd_printf("\fSPI Collision 1\r\n");
hal_printf("\fSPI Collision 1\r\n");
HARD_BREAKPOINT();
return FALSE;
}
// first build the mode register
SPI.CONTROLREG = MC9328MXL_SPI::ConfigurationToMode( Configuration );
// LCD Controller needs to have Pulse mode enabled
#if (HARDWARE_BOARD_TYPE >= HARDWARE_BOARD_i_MXS_DEMO_REV_V1_2)
if(Configuration.DeviceCS == MC9328MXL_SPI::c_SPI1_SS)
{
SPI.PERIODREG = 2;
SPI.CONTROLREG |= MC9328MXL_SPI::CONTROLREG_SSCTL_PULSE; // Pulse SS between bursts
// set the SSPOL to active lo as it is force at the ConfigurationMOde to not trigger SS for other SPI operation
SPI.CONTROLREG &= (~MC9328MXL_SPI::CONTROLREG_SSPOL_HIGH); // Pulse SS between bursts
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_SS,RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
}
#endif
SPI.CONTROLREG |= MC9328MXL_SPI::CONTROLREG_SPIEN;
#if (SPI_LOOP_BACK)
// for spi testing
SPI.TESTREG |= SPI.TESTREG_LBC;
#endif
// everything should be clean and idle
ASSERT( SPI.TransmitBufferEmpty());
ASSERT( SPI.ReceiveBufferEmpty());
ASSERT( SPI.ShiftBufferEmpty ());
// make sure not trigger the SS pin for the LCD when doing any SPI activity.
// but we can have LCD SPI activity, if so, we want the SS be able to drive
#if (HARDWARE_BOARD_TYPE >= HARDWARE_BOARD_i_MXS_DEMO_REV_V1_2)
if(Configuration.DeviceCS != MC9328MXL_SPI::c_SPI1_SS)
{
CPU_GPIO_EnableInputPin( MC9328MXL_SPI::c_SPI1_SS, FALSE, NULL, GPIO_INT_NONE, RESISTOR_PULLUP );
}
#endif
#if defined(PLATFORM_ARM_MC9328MXS)
// make sure that we don't trigger the SS pin for LCD
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_SCLK, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_MOSI, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
#else // MC9328MXL
if (index == MC9328MXL_SPI::c_SPI1)
{
// allow peripheral control of pins
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_SCLK, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_MOSI, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
}
else
{
// SPI2 need to set to Alternate function - AIN
CPU_GPIO_DisablePin(MC9328MXL_SPI::c_SPI2_SCLK, RESISTOR_DISABLED, MC9328MXL_GPIO::DDIR__OUT, GPIO_ALT_MODE_1);
CPU_GPIO_DisablePin(MC9328MXL_SPI::c_SPI2_MOSI, RESISTOR_DISABLED, MC9328MXL_GPIO::DDIR__OUT, GPIO_ALT_MODE_1);
}
#endif
// first set CS active as soon as clock and data pins are in proper initial state
if((Configuration.DeviceCS != MC9328MXL_GPIO::c_Pin_None) && (Configuration.DeviceCS != MC9328MXL_SPI::c_SPI1_SS))
{
CPU_GPIO_EnableOutputPin( Configuration.DeviceCS, Configuration.CS_Active );
}
#if defined(PLATFORM_ARM_MC9328MXS)
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_MISO, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY );
#else
if (index == MC9328MXL_SPI::c_SPI1)
{
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_MISO, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY );
}
else
{
// set AOUT mode for MISO for SPI 2
CPU_GPIO_DisablePin(MC9328MXL_SPI::c_SPI2_MISO, RESISTOR_DISABLED,MC9328MXL_GPIO::DDIR__IN ,GPIO_ALT_MODE_4);
MC9328MXL::SC().FMCR |= MC9328MXL_SC::FMCR__SPI2_RXD_SEL;
}
#endif
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Setup_uSecs );
}
}
else
{
lcd_printf( "\fSPI Collision 3\r\n" );
HARD_BREAKPOINT();
return FALSE;
}
return TRUE;
}
BOOL PXA271_SPI_Driver::Xaction_Stop( const SPI_CONFIGURATION& Configuration )
{
if(g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].m_Enabled)
{
PXA271_SPI& SPI = PXA271::SPI(Configuration.SPI_mod);
// we should have cleared the last TBF on the last RBF true setting
// we should never bring CS inactive with the shifter busy
ASSERT(!SPI.TransmitFifoNotEmpty());
ASSERT( SPI.ReceiveFifoEmpty());
ASSERT( SPI.ShiftBufferEmpty());
if(Configuration.CS_Hold_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Hold_uSecs );
}
// avoid noise drawing excess power on a floating line by putting this in pulldown
if(Configuration.SPI_mod ==0)
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_1);
else if(Configuration.SPI_mod ==1)
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_2);
else
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_3);
// next, bring the CS to the proper inactive state
if(Configuration.DeviceCS != PXA271_GPIO::c_Pin_None)
{
CPU_GPIO_EnableOutputPin(Configuration.DeviceCS, !Configuration.CS_Active);
}
// put pins in output low state when not in use to avoid noise since clock stop and reset will cause these to become inputs
if(Configuration.SPI_mod ==0)
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
}
else if(Configuration.SPI_mod ==1)
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
}
else
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
}
// disable spi bus so no new operations start
SPI.SSP_SSCR0 = 0;
SPI.SSP_SSCR1 = 0;
PXA271::CLKMNGR().CKEN &= ~g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].ClockIndex;
g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].m_Enabled = FALSE;
}
else
{
lcd_printf("\fSPI Collision 4\r\n");
HARD_BREAKPOINT();
return FALSE;
}
return TRUE;
}
BOOL PXA271_SPI_Driver::Xaction_Start( const SPI_CONFIGURATION& Configuration )
{
if(!g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].m_Enabled)
{
g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].m_Enabled= TRUE;
// enable the Periperal clock for this device
PXA271::CLKMNGR().CKEN |= g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].ClockIndex;
PXA271_SPI& SPI = PXA271::SPI(Configuration.SPI_mod);
// make sure we didn't start one in the middle of an existing transaction
if((0 != SPI.SSP_SSCR0)||(0 != SPI.SSP_SSCR1))
{
lcd_printf("\fSPI Collision 1\r\n");
HARD_BREAKPOINT();
return FALSE;
}
SPI.SSP_SSCR0= PXA271_SPI::ConfigurationControlReg0( Configuration );
SPI.SSP_SSCR1= PXA271_SPI::ConfigurationControlReg1( Configuration );
#ifdef SPI_LOOP_BACK_PXA271
SPI.SSP_SSCR1|= SPI_LOOPBACK;
#endif
SPI.SSP_SSCR0|= SPI.SSP_SSCR0__SSE;
//everything should be clean and idle
ASSERT(!SPI.TransmitFifoNotEmpty());
ASSERT( SPI.ReceiveFifoEmpty());
ASSERT( SPI.ShiftBufferEmpty());
if(Configuration.SPI_mod ==0)
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
}
else if(Configuration.SPI_mod ==1)
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
}
else
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
}
// first set CS active as soon as clock and data pins are in proper initial state
if(Configuration.DeviceCS != PXA271_GPIO::c_Pin_None)
{
CPU_GPIO_EnableOutputPin(Configuration.DeviceCS, Configuration.CS_Active);
}
if(Configuration.SPI_mod ==0)
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_1);
else if(Configuration.SPI_mod ==1)
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_2);
else
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_3);
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Setup_uSecs );
}
}
else
{
lcd_printf( "\fSPI Collision 3\r\n" );
HARD_BREAKPOINT();
return FALSE;
}
return TRUE;
}
void __section("SectionForBootstrapOperations") BootstrapCode_GPIO()
{
/* GPIO pins connected to NOR Flash and SRAM on the MCBSTM32F400 board */
const uint8_t PortD_PinList[] = {0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12 ,13, 14, 15};
#ifdef DEBUG
// PE2,3,4,5 are used for TRACECLK and TRACEDATA0-3 so don't enable them as address pins in debug builds
// This limits external FLASH and SRAM to 1MB addressable space each.
const uint8_t PortE_PinList[] = {0, 1, /*2, 3, 4, 5,*/ 7, 8, 9, 10, 11, 12, 13, 14, 15};
#else
const uint8_t PortE_PinList[] = {0, 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15};
#endif
const uint8_t PortF_PinList[] = {0, 1, 2, 3, 4, 5, 12, 13, 14, 15};
const uint8_t PortG_PinList[] = {0, 1, 2, 3, 4, 5, 10};
const uint32_t pinConfig = 0x3C2; // Speed 100Mhz, AF12 FSMC, Alternate Mode
const uint32_t pinMode = pinConfig & 0xF;
const GPIO_ALT_MODE alternateMode = (GPIO_ALT_MODE) pinConfig;
const GPIO_RESISTOR resistorConfig = RESISTOR_PULLUP;
uint32_t i;
/* Enable GPIO clocks */
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN
| RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN;
CPU_GPIO_EnableOutputPin(LED1, FALSE);
CPU_GPIO_EnableOutputPin(LED2, FALSE);
CPU_GPIO_EnableOutputPin(LED3, FALSE);
CPU_GPIO_EnableOutputPin(LED4, FALSE);
CPU_GPIO_EnableOutputPin(LED5, FALSE);
CPU_GPIO_EnableOutputPin(LED6, FALSE);
CPU_GPIO_EnableOutputPin(LED7, FALSE);
CPU_GPIO_EnableOutputPin(LED8, FALSE);
/*Initialize SRAM and NOR GPIOs */
for(i = 0; i < ARRAY_LENGTH(PortD_PinList); i++) /* Port D */
{
CPU_GPIO_ReservePin( PORT_PIN(GPIO_PORTD, PortD_PinList[i]), TRUE);
CPU_GPIO_DisablePin( PORT_PIN(GPIO_PORTD, PortD_PinList[i]), resistorConfig, 0, alternateMode);
STM32F4_GPIO_Pin_Config( PORT_PIN(GPIO_PORTD, PortD_PinList[i]), pinMode, resistorConfig, pinConfig ); // Workaround, since CPU_GPIO_DisablePin() does not correctly initialize pin speeds
}
for(i = 0; i < ARRAY_LENGTH(PortE_PinList); i++) /* Port E */
{
CPU_GPIO_ReservePin( PORT_PIN(GPIO_PORTE, PortE_PinList[i]), TRUE);
CPU_GPIO_DisablePin( PORT_PIN(GPIO_PORTE, PortE_PinList[i]), resistorConfig, 0, alternateMode);
STM32F4_GPIO_Pin_Config( PORT_PIN(GPIO_PORTE, PortE_PinList[i]), pinMode, resistorConfig, pinConfig ); // Workaround, since CPU_GPIO_DisablePin() does not correctly initialize pin speeds
}
for(i = 0; i < ARRAY_LENGTH(PortF_PinList); i++) /* Port F */
{
CPU_GPIO_ReservePin( PORT_PIN(GPIO_PORTF, PortF_PinList[i]), TRUE);
CPU_GPIO_DisablePin( PORT_PIN(GPIO_PORTF, PortF_PinList[i]), resistorConfig, 0, alternateMode);
STM32F4_GPIO_Pin_Config( PORT_PIN(GPIO_PORTF, PortF_PinList[i]), pinMode, resistorConfig, pinConfig ); // Workaround, since CPU_GPIO_DisablePin() does not correctly initialize pin speeds
}
for(i = 0; i < ARRAY_LENGTH(PortG_PinList); i++) /* Port G */
{
CPU_GPIO_ReservePin( PORT_PIN(GPIO_PORTG, PortG_PinList[i]), TRUE);
CPU_GPIO_DisablePin( PORT_PIN(GPIO_PORTG, PortG_PinList[i]), resistorConfig, 0, alternateMode);
STM32F4_GPIO_Pin_Config( PORT_PIN(GPIO_PORTG, PortG_PinList[i]), pinMode, resistorConfig, pinConfig ); // Workaround, since CPU_GPIO_DisablePin() does not correctly initialize pin speeds
}
/* Initialize NOR and SRAM */
InitNorFlash();
InitSram();
}
void PXA271_USART_Driver::ProtectPins( int comPort, BOOL on )
{
struct PXA271_USART_CONFIG* Config = &g_PXA271_USART_Config;
if(comPort < 0 || comPort >= TOTAL_USART_PORT)
return;
USART_PORT_INFO& USART_port = All_USART_ports[comPort];
GLOBAL_LOCK(irq);
if(on)
{
if(!USART_port.PinsProtected)
{
USART_port.PinsProtected = TRUE;
RxBufferFullInterruptEnable( comPort, FALSE );
if(Config->RxProtectInput)
{
CPU_GPIO_EnableInputPin( USART_port.RXD_Pin, FALSE, NULL, GPIO_INT_NONE, Config->RxProtectResistor );
}
else
{
CPU_GPIO_EnableOutputPin( USART_port.RXD_Pin, Config->RxProtectOutputValue );
}
TxBufferEmptyInterruptEnable( comPort, FALSE );
if(Config->TxProtectInput)
{
CPU_GPIO_EnableInputPin( USART_port.TXD_Pin, FALSE, NULL, GPIO_INT_NONE, Config->TxProtectResistor );
}
else
{
CPU_GPIO_EnableOutputPin( USART_port.TXD_Pin, Config->TxProtectOutputValue );
}
if(USART_port.CTS_Pin_used)
{
if(Config->CTSProtectInput)
{
CPU_GPIO_EnableInputPin( USART_port.CTS_Pin, FALSE, NULL, GPIO_INT_NONE, Config->CTSProtectResistor );
}
else
{
CPU_GPIO_EnableOutputPin( USART_port.CTS_Pin, Config->CTSProtectOutputValue );
}
}
if(USART_port.RTS_Pin_used)
{
if(Config->RTSProtectInput)
{
CPU_GPIO_EnableInputPin( USART_port.RTS_Pin, FALSE, NULL, GPIO_INT_NONE, Config->RTSProtectResistor );
}
else
{
CPU_GPIO_EnableOutputPin( USART_port.RTS_Pin, Config->RTSProtectOutputValue );
}
}
}
}
else
{
if(USART_port.PinsProtected)
{
USART_port.PinsProtected = FALSE;
CPU_GPIO_DisablePin( USART_port.TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT, USART_port.TXD_Pin_function );
TxBufferEmptyInterruptEnable( comPort, TRUE );
CPU_GPIO_DisablePin( USART_port.RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN, USART_port.RXD_Pin_function );
RxBufferFullInterruptEnable( comPort, TRUE );
if(USART_port.CTS_Pin_used)
CPU_GPIO_DisablePin( USART_port.CTS_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN, USART_port.CTS_Pin_function );
if(USART_port.RTS_Pin_used)
CPU_GPIO_DisablePin( USART_port.RTS_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT, USART_port.RTS_Pin_function );
}
}
}
//Initialize USB Host
// USB OTG Full Speed is controller 0
// USB OTG High Speed is controller 1
BOOL USBH_Initialize( int Controller ) {
CPU_GPIO_EnableOutputPin(16+2, TRUE);
// enable USB clock
OTG_TypeDef* OTG;
if (Controller == 0) {
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
OTG = OTG_FS;
}
else if (Controller == 1) {
RCC->AHB1ENR |= RCC_AHB1ENR_OTGHSEN;
OTG = OTG_HS;
}
else {
return FALSE;
}
//disable int
OTG->GAHBCFG &= ~OTG_GAHBCFG_GINTMSK;
//core init 1
OTG->GINTSTS |= OTG_GINTSTS_RXFLVL;
OTG->GAHBCFG |= OTG_GAHBCFG_PTXFELVL;
//core init 2
OTG->GUSBCFG &= ~OTG_GUSBCFG_HNPCAP;
OTG->GUSBCFG &= ~OTG_GUSBCFG_SRPCAP;
OTG->GUSBCFG &= ~OTG_GUSBCFG_TRDT;
OTG->GUSBCFG |= STM32F4_USB_TRDT<<10;
OTG->GUSBCFG |= OTG_GUSBCFG_PHYSEL;
//core init 3
OTG->GINTMSK |= OTG_GINTMSK_OTGINT | OTG_GINTMSK_MMISM;
//force host mode
OTG->GUSBCFG |= OTG_GUSBCFG_FHMOD;
//host init
OTG->GINTMSK |= OTG_GINTMSK_PRTIM;
OTG->HCFG = OTG_HCFG_FSLSPCS_48MHZ;
OTG->HPRT |= OTG_HPRT_PPWR;
OTG->GCCFG |= (OTG_GCCFG_VBUSBSEN | OTG_GCCFG_VBUSASEN | OTG_GCCFG_NOVBUSSENS | OTG_GCCFG_PWRDWN);
//
//config pins and ISR
if (Controller == 0) {
CPU_GPIO_DisablePin(10, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)0xA2);
CPU_GPIO_DisablePin(11, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)0xA2);
CPU_INTC_ActivateInterrupt(OTG_FS_IRQn, USBH_ISR, OTG);
}
else {
CPU_GPIO_DisablePin(16+14, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)0xC2);
CPU_GPIO_DisablePin(16+15, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)0xC2);
CPU_INTC_ActivateInterrupt(OTG_HS_IRQn, USBH_ISR, OTG);
}
for (int i = 0; i < 3; i++)
{
CPU_GPIO_SetPinState(18, 1);
HAL_Time_Sleep_MicroSeconds(200*1000);
CPU_GPIO_SetPinState(18, 0);
HAL_Time_Sleep_MicroSeconds(200*1000);
}
//enable interrupt
OTG->GINTSTS = 0xFFFFFFFF;
OTG->GAHBCFG |= OTG_GAHBCFG_GINTMSK;
return TRUE;
}
