void * kse_init(unsigned tag, void *data) { struct local *l; struct desc *txd, *rxd; unsigned i, val, fdx; uint8_t *en; l = ALLOC(struct local, sizeof(struct desc)); /* desc alignment */ memset(l, 0, sizeof(struct local)); l->csr = DEVTOV(pcicfgread(tag, 0x10)); en = data; i = CSR_READ_2(l, MARL); en[0] = i; en[1] = i >> 8; i = CSR_READ_2(l, MARM); en[2] = i; en[3] = i >> 8; i = CSR_READ_2(l, MARH); en[4] = i; en[5] = i >> 8; printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", en[0], en[1], en[2], en[3], en[4], en[5]); CSR_WRITE_2(l, CIDR, 1); mii_dealan(l, 5); val = pcicfgread(tag, PCI_ID_REG); if (PCI_PRODUCT(val) == 0x8841) { val = CSR_READ_4(l, P1SR); fdx = !!(val & (1U << 9)); printf("%s", (val & (1U << 8)) ? "100Mbps" : "10Mbps"); if (fdx) printf("-FDX"); printf("\n"); } txd = &l->txd; rxd = &l->rxd[0]; rxd[0].xd0 = htole32(R0_OWN); rxd[0].xd1 = htole32(FRAMESIZE); rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0])); rxd[0].xd3 = htole32(VTOPHYS(&rxd[1])); rxd[1].xd0 = htole32(R0_OWN); rxd[1].xd1 = htole32(R1_RER | FRAMESIZE); rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1])); rxd[1].xd3 = htole32(VTOPHYS(&rxd[0])); l->rx = 0; CSR_WRITE_4(l, TDLB, VTOPHYS(txd)); CSR_WRITE_4(l, RDLB, VTOPHYS(rxd)); CSR_WRITE_4(l, MDTXC, 07); /* stretch short, add CRC, Tx enable */ CSR_WRITE_4(l, MDRXC, 01); /* Rx enable */ CSR_WRITE_4(l, MDRSC, 01); /* start receiving */ return l; }
int an_alloc_nicmem(struct an_softc *sc, int len, int *idp) { int i; if (an_cmd(sc, AN_CMD_ALLOC_MEM, len)) { printf("%s: failed to allocate %d bytes on NIC\n", sc->sc_dev.dv_xname, len); return(ENOMEM); } for (i = 0; i < AN_TIMEOUT; i++) { if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_ALLOC) break; if (i == AN_TIMEOUT) { printf("%s: timeout in alloc\n", sc->sc_dev.dv_xname); return ETIMEDOUT; } DELAY(10); } *idp = CSR_READ_2(sc, AN_ALLOC_FID); CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_ALLOC); return 0; }
int ste_intr(void *xsc) { struct ste_softc *sc; struct ifnet *ifp; u_int16_t status; int claimed = 0; sc = xsc; ifp = &sc->arpcom.ac_if; /* See if this is really our interrupt. */ if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) return claimed; for (;;) { status = CSR_READ_2(sc, STE_ISR_ACK); if (!(status & STE_INTRS)) break; claimed = 1; if (status & STE_ISR_RX_DMADONE) { ste_rxeoc(sc); ste_rxeof(sc); } if (status & STE_ISR_TX_DMADONE) ste_txeof(sc); if (status & STE_ISR_TX_DONE) ste_txeoc(sc); if (status & STE_ISR_STATS_OFLOW) { timeout_del(&sc->sc_stats_tmo); ste_stats_update(sc); } if (status & STE_ISR_LINKEVENT) mii_pollstat(&sc->sc_mii); if (status & STE_ISR_HOSTERR) { ste_reset(sc); ste_init(sc); } } /* Re-enable interrupts */ CSR_WRITE_2(sc, STE_IMR, STE_INTRS); if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) ste_start(ifp); return claimed; }
int an_intr(void *arg) { struct an_softc *sc = arg; struct ifnet *ifp = &sc->sc_ic.ic_if; int i; u_int16_t status; if (!sc->sc_enabled || sc->sc_invalid || (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || (ifp->if_flags & IFF_RUNNING) == 0) return 0; if ((ifp->if_flags & IFF_UP) == 0) { CSR_WRITE_2(sc, AN_INT_EN, 0); CSR_WRITE_2(sc, AN_EVENT_ACK, ~0); return 1; } /* maximum 10 loops per interrupt */ for (i = 0; i < 10; i++) { if (!sc->sc_enabled || sc->sc_invalid) return 1; if (CSR_READ_2(sc, AN_SW0) != AN_MAGIC) { DPRINTF(("an_intr: magic number changed: %x\n", CSR_READ_2(sc, AN_SW0))); sc->sc_invalid = 1; return 1; } status = CSR_READ_2(sc, AN_EVENT_STAT); CSR_WRITE_2(sc, AN_EVENT_ACK, status & ~(AN_INTRS)); if ((status & AN_INTRS) == 0) break; if (status & AN_EV_RX) an_rxeof(sc); if (status & (AN_EV_TX | AN_EV_TX_EXC)) an_txeof(sc, status); if (status & AN_EV_LINKSTAT) an_linkstat_intr(sc); if (ifq_is_oactive(&ifp->if_snd) == 0 && sc->sc_ic.ic_state == IEEE80211_S_RUN && !IFQ_IS_EMPTY(&ifp->if_snd)) an_start(ifp); } return 1; }
static void dump_regs(Environ *e, Self *s) { dprintf("\n"); dprintf("ethxpro: scb_rus/scb_cus: %#x\n", CSR_READ_1(s, CSR_SCB_RUSCUS)); dprintf("ethxpro: scb_statack: %#x\n", CSR_READ_1(s, CSR_SCB_STATACK)); dprintf("ethxpro: scb_command: %#x\n", CSR_READ_1(s, CSR_SCB_COMMAND)); dprintf("ethxpro: scb_intrcntl: %#x\n", CSR_READ_1(s, CSR_SCB_INTRCNTL)); dprintf("ethxpro: scb_general: %#x\n", CSR_READ_4(s, CSR_SCB_GENERAL)); dprintf("ethxpro: port: %#x\n", CSR_READ_4(s, CSR_PORT)); dprintf("ethxpro: flash control: %#x\n", CSR_READ_2(s, CSR_FLASHCONTROL)); dprintf("ethxpro: eeprom ctrl: %#x\n", CSR_READ_2(s, CSR_EEPROMCONTROL)); dprintf("ethxpro: mdi control: %#x\n", CSR_READ_4(s, CSR_MDICONTROL)); }
static void vr_reset(struct vr_softc *sc) { int i; VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); for (i = 0; i < VR_TIMEOUT; i++) { DELAY(10); if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) break; } if (i == VR_TIMEOUT) { if (sc->vr_revid < REV_ID_VT3065_A) { printf("%s: reset never completed!\n", device_xname(sc->vr_dev)); } else { /* Use newer force reset command */ printf("%s: using force reset command.\n", device_xname(sc->vr_dev)); VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); } } /* Wait a little while for the chip to get its brains in order. */ DELAY(1000); }
int an_seek_bap(struct an_softc *sc, int id, int off) { int i, status; CSR_WRITE_2(sc, AN_SEL0, id); CSR_WRITE_2(sc, AN_OFF0, off); for (i = 0; ; i++) { status = CSR_READ_2(sc, AN_OFF0); if ((status & AN_OFF_BUSY) == 0) break; if (i == AN_TIMEOUT) { printf("%s: timeout in an_seek_bap to 0x%x/0x%x\n", sc->sc_dev.dv_xname, id, off); sc->sc_bap_off = AN_OFF_ERR; /* invalidate */ return ETIMEDOUT; } DELAY(10); } if (status & AN_OFF_ERR) { printf("%s: failed in an_seek_bap to 0x%x/0x%x\n", sc->sc_dev.dv_xname, id, off); sc->sc_bap_off = AN_OFF_ERR; /* invalidate */ return EIO; } sc->sc_bap_id = id; sc->sc_bap_off = off; return 0; }
static void ex_probemedia(void) { int i, j; struct mtabentry *m; /* test for presence of connectors */ GO_WINDOW(3); i = CSR_READ_1(ELINK_W3_RESET_OPTIONS); j = (CSR_READ_2(ELINK_W3_INTERNAL_CONFIG + 2) & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; GO_WINDOW(0); for (ether_medium = 0, m = mediatab; ether_medium < sizeof(mediatab) / sizeof(mediatab[0]); ether_medium++, m++) { if (j == m->address_cfg) { if (!(i & m->config_bit)) { printf("%s not present\n", m->name); goto bad; } printf("using %s\n", m->name); return; } } printf("unknown connector\n"); bad: ether_medium = -1; }
void ste_miibus_statchg(struct device *self) { struct ste_softc *sc = (struct ste_softc *)self; struct mii_data *mii; int fdx, fcur; mii = &sc->sc_mii; fcur = CSR_READ_2(sc, STE_MACCTL0) & STE_MACCTL0_FULLDUPLEX; fdx = (mii->mii_media_active & IFM_GMASK) == IFM_FDX; if ((fcur && fdx) || (! fcur && ! fdx)) return; STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL |STE_DMACTL_TXDMA_STALL); ste_wait(sc); if (fdx) STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); else STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL | STE_DMACTL_TXDMA_UNSTALL); return; }
static void wi_pci_reset(struct wi_softc *sc) { int i, secs, usecs; bus_space_write_2(sc->sc_iot, sc->sc_ioh, WI_PCI_COR, WI_COR_SOFT_RESET); DELAY(250*1000); /* 1/4 second */ bus_space_write_2(sc->sc_iot, sc->sc_ioh, WI_PCI_COR, WI_COR_CLEAR); DELAY(500*1000); /* 1/2 second */ /* wait 2 seconds for firmware to complete initialization. */ for (i = 200000; i--; DELAY(10)) if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) break; if (i < 0) { printf("%s: PCI reset timed out\n", device_xname(sc->sc_dev)); } else if (sc->sc_if.if_flags & IFF_DEBUG) { usecs = (200000 - i) * 10; secs = usecs / 1000000; usecs %= 1000000; printf("%s: PCI reset in %d.%06d seconds\n", device_xname(sc->sc_dev), secs, usecs); } return; }
static int wi_pcmcia_load_firm(struct wi_softc *sc, const void *primsym, int primlen, const void *secsym, int seclen) { u_int8_t ebuf[256]; int i; /* load primary code and run it */ wi_pcmcia_set_hcr(sc, WI_HCR_EEHOLD); if (wi_pcmcia_write_firm(sc, primsym, primlen, NULL, 0)) return EIO; wi_pcmcia_set_hcr(sc, WI_HCR_RUN); for (i = 0; ; i++) { if (i == 10) return ETIMEDOUT; tsleep(sc, PWAIT, "wiinit", 1); if (CSR_READ_2(sc, WI_CNTL) == WI_CNTL_AUX_ENA_STAT) break; /* write the magic key value to unlock aux port */ CSR_WRITE_2(sc, WI_PARAM0, WI_AUX_KEY0); CSR_WRITE_2(sc, WI_PARAM1, WI_AUX_KEY1); CSR_WRITE_2(sc, WI_PARAM2, WI_AUX_KEY2); CSR_WRITE_2(sc, WI_CNTL, WI_CNTL_AUX_ENA_CNTL); } /* issue read EEPROM command: XXX copied from wi_cmd() */ CSR_WRITE_2(sc, WI_PARAM0, 0); CSR_WRITE_2(sc, WI_PARAM1, 0); CSR_WRITE_2(sc, WI_PARAM2, 0); CSR_WRITE_2(sc, WI_COMMAND, WI_CMD_READEE); for (i = 0; i < WI_TIMEOUT; i++) { if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD) break; DELAY(1); } CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD); CSR_WRITE_2(sc, WI_AUX_PAGE, WI_SBCF_PDIADDR / WI_AUX_PGSZ); CSR_WRITE_2(sc, WI_AUX_OFFSET, WI_SBCF_PDIADDR % WI_AUX_PGSZ); CSR_READ_MULTI_STREAM_2(sc, WI_AUX_DATA, (u_int16_t *)ebuf, sizeof(ebuf) / 2); if (GETLE16(ebuf) > sizeof(ebuf)) return EIO; if (wi_pcmcia_write_firm(sc, secsym, seclen, ebuf + 4, GETLE16(ebuf))) return EIO; return 0; }
void ex_set_media(void) { int config0, config1; CSR_WRITE_2(ELINK_W3_MAC_CONTROL, 0); if (ether_medium == ETHERMEDIUM_MII) goto setcfg; GO_WINDOW(4); CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, 0); CSR_WRITE_2(ELINK_COMMAND, STOP_TRANSCEIVER); delay(800); switch (ether_medium) { case ETHERMEDIUM_UTP: CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, JABBER_GUARD_ENABLE | LINKBEAT_ENABLE); break; case ETHERMEDIUM_BNC: CSR_WRITE_2(ELINK_COMMAND, START_TRANSCEIVER); delay(800); break; case ETHERMEDIUM_AUI: CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, SQE_ENABLE); delay(800); break; case ETHERMEDIUM_100TX: CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, LINKBEAT_ENABLE); break; } setcfg: GO_WINDOW(3); config0 = CSR_READ_2(ELINK_W3_INTERNAL_CONFIG); config1 = CSR_READ_2(ELINK_W3_INTERNAL_CONFIG + 2); config1 = config1 & ~CONFIG_MEDIAMASK; config1 |= (mediatab[ether_medium].address_cfg << CONFIG_MEDIAMASK_SHIFT); CSR_WRITE_2(ELINK_W3_INTERNAL_CONFIG, config0); CSR_WRITE_2(ELINK_W3_INTERNAL_CONFIG + 2, config1); }
/* Must be called at proper protection level! */ int an_cmd(struct an_softc *sc, int cmd, int val) { int i, stat; /* make sure previous command completed */ if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY) { if (sc->sc_ic.ic_if.if_flags & IFF_DEBUG) printf("%s: command 0x%x busy\n", sc->sc_dev.dv_xname, CSR_READ_2(sc, AN_COMMAND)); CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY); } CSR_WRITE_2(sc, AN_PARAM0, val); CSR_WRITE_2(sc, AN_PARAM1, 0); CSR_WRITE_2(sc, AN_PARAM2, 0); CSR_WRITE_2(sc, AN_COMMAND, cmd); if (cmd == AN_CMD_FW_RESTART) { /* XXX: should sleep here */ DELAY(100*1000); } for (i = 0; i < AN_TIMEOUT; i++) { if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD) break; DELAY(10); } stat = CSR_READ_2(sc, AN_STATUS); /* clear stuck command busy if necessary */ if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY) CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY); /* Ack the command */ CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD); if (i == AN_TIMEOUT) { if (sc->sc_ic.ic_if.if_flags & IFF_DEBUG) printf("%s: command 0x%x param 0x%x timeout\n", sc->sc_dev.dv_xname, cmd, val); return ETIMEDOUT; } if (stat & AN_STAT_CMD_RESULT) { if (sc->sc_ic.ic_if.if_flags & IFF_DEBUG) printf("%s: command 0x%x param 0x%x status 0x%x " "resp 0x%x 0x%x 0x%x\n", sc->sc_dev.dv_xname, cmd, val, stat, CSR_READ_2(sc, AN_RESP0), CSR_READ_2(sc, AN_RESP1), CSR_READ_2(sc, AN_RESP2)); return EIO; } return 0; }
uint16_t bwi_phy_read(struct bwi_mac *mac, uint16_t ctrl) { struct bwi_softc *sc = mac->mac_sc; CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl); return CSR_READ_2(sc, BWI_PHY_DATA); }
int rtk_intr(void *arg) { struct rtk_softc *sc; struct ifnet *ifp; uint16_t status; int handled; sc = arg; ifp = &sc->ethercom.ec_if; if (!device_has_power(sc->sc_dev)) return 0; /* Disable interrupts. */ CSR_WRITE_2(sc, RTK_IMR, 0x0000); handled = 0; for (;;) { status = CSR_READ_2(sc, RTK_ISR); if (status == 0xffff) break; /* Card is gone... */ if (status) CSR_WRITE_2(sc, RTK_ISR, status); if ((status & RTK_INTRS) == 0) break; handled = 1; if (status & RTK_ISR_RX_OK) rtk_rxeof(sc); if (status & RTK_ISR_RX_ERR) rtk_rxeof(sc); if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) rtk_txeof(sc); if (status & RTK_ISR_SYSTEM_ERR) { rtk_reset(sc); rtk_init(ifp); } } /* Re-enable interrupts. */ CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) rtk_start(ifp); rnd_add_uint32(&sc->rnd_source, status); return handled; }
static void vr_mii_statchg(struct ifnet *ifp) { struct vr_softc *sc = ifp->if_softc; int i; /* * In order to fiddle with the 'full-duplex' bit in the netconfig * register, we first have to put the transmit and/or receive logic * in the idle state. */ if ((sc->vr_mii.mii_media_status & IFM_ACTIVE) && IFM_SUBTYPE(sc->vr_mii.mii_media_active) != IFM_NONE) { sc->vr_link = true; if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); if (sc->vr_mii.mii_media_active & IFM_FDX) VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); else VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); } else { sc->vr_link = false; VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); for (i = VR_TIMEOUT; i > 0; i--) { delay(10); if (!(CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON))) break; } if (i == 0) { #ifdef VR_DEBUG printf("%s: rx shutdown error!\n", device_xname(sc->vr_dev)); #endif sc->vr_flags |= VR_F_RESTART; } } }
void vte_get_macaddr(struct vte_softc *sc) { uint16_t mid; /* * It seems there is no way to reload station address and * it is supposed to be set by BIOS. */ mid = CSR_READ_2(sc, VTE_MID0L); sc->vte_eaddr[0] = (mid >> 0) & 0xFF; sc->vte_eaddr[1] = (mid >> 8) & 0xFF; mid = CSR_READ_2(sc, VTE_MID0M); sc->vte_eaddr[2] = (mid >> 0) & 0xFF; sc->vte_eaddr[3] = (mid >> 8) & 0xFF; mid = CSR_READ_2(sc, VTE_MID0H); sc->vte_eaddr[4] = (mid >> 0) & 0xFF; sc->vte_eaddr[5] = (mid >> 8) & 0xFF; }
static uint16_t pcn_bcr_read16(pcn_t *pcnp, uint32_t reg) { uint16_t val; mutex_enter(&pcnp->pcn_reglock); CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg); val = CSR_READ_2(pcnp, PCN_IO16_BDP); mutex_exit(&pcnp->pcn_reglock); return (val); }
int vte_miibus_readreg(struct device *dev, int phy, int reg) { struct vte_softc *sc = (struct vte_softc *)dev; int i; CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); for (i = VTE_PHY_TIMEOUT; i > 0; i--) { DELAY(5); if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) break; } if (i == 0) { printf("%s: phy read timeout: phy %d, reg %d\n", sc->sc_dev.dv_xname, phy, reg); return (0); } return (CSR_READ_2(sc, VTE_MMRD)); }
static int ex_eeprom_busy(void) { int i = 100; while (i--) { if (!(CSR_READ_2(ELINK_W0_EEPROM_COMMAND) & EEPROM_BUSY)) return 0; delay(100); } printf("\nex: eeprom stays busy.\n"); return 1; }
/* * Wait for firmware come up after power enabled. */ void an_wait(struct an_softc *sc) { int i; CSR_WRITE_2(sc, AN_COMMAND, AN_CMD_NOOP2); for (i = 0; i < 3*hz; i++) { if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD) break; (void)tsleep(sc, PWAIT, "anatch", 1); } CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD); }
int __haiku_disable_interrupts(device_t dev) { struct xl_softc *sc = device_get_softc(dev); u_int16_t status = CSR_READ_2(sc, XL_STATUS); if (status == 0xffff || (status & XL_INTRS) == 0) return 0; CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB); CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | (status & XL_INTRS)); atomic_set((int32 *)&sc->xl_intr_status, status); return 1; }
/* * Read EEPROM data. * XXX what to do if EEPROM doesn't unbusy? */ uint16_t ex_read_eeprom(int offset) { uint16_t data = 0; GO_WINDOW(0); if (ex_eeprom_busy()) goto out; CSR_WRITE_1(ELINK_W0_EEPROM_COMMAND, READ_EEPROM | (offset & 0x3f)); if (ex_eeprom_busy()) goto out; data = CSR_READ_2(ELINK_W0_EEPROM_DATA); out: return data; }
static int wi_pcmcia_set_hcr(struct wi_softc *sc, int mode) { u_int16_t hcr; CSR_WRITE_2(sc, WI_COR, WI_COR_RESET); tsleep(sc, PWAIT, "wiinit", 1); hcr = CSR_READ_2(sc, WI_HCR); hcr = (hcr & WI_HCR_4WIRE) | (mode & ~WI_HCR_4WIRE); CSR_WRITE_2(sc, WI_HCR, hcr); tsleep(sc, PWAIT, "wiinit", 1); CSR_WRITE_2(sc, WI_COR, WI_COR_IOMODE); tsleep(sc, PWAIT, "wiinit", 1); return 0; }
static int rtk_phy_readreg(device_t self, int phy, int reg) { struct rtk_softc *sc = device_private(self); struct rtk_mii_frame frame; int rval; int rtk8139_reg; if ((sc->sc_quirk & RTKQ_8129) == 0) { if (phy != 7) return 0; switch (reg) { case MII_BMCR: rtk8139_reg = RTK_BMCR; break; case MII_BMSR: rtk8139_reg = RTK_BMSR; break; case MII_ANAR: rtk8139_reg = RTK_ANAR; break; case MII_ANER: rtk8139_reg = RTK_ANER; break; case MII_ANLPAR: rtk8139_reg = RTK_LPAR; break; default: #if 0 printf("%s: bad phy register\n", device_xname(self)); #endif return 0; } rval = CSR_READ_2(sc, rtk8139_reg); return rval; } memset(&frame, 0, sizeof(frame)); frame.mii_phyaddr = phy; frame.mii_regaddr = reg; rtk_mii_readreg(sc, &frame); return frame.mii_data; }
void vte_miibus_writereg(struct device *dev, int phy, int reg, int val) { struct vte_softc *sc = (struct vte_softc *)dev; int i; CSR_WRITE_2(sc, VTE_MMWD, val); CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); for (i = VTE_PHY_TIMEOUT; i > 0; i--) { DELAY(5); if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) break; } if (i == 0) printf("%s: phy write timeout: phy %d, reg %d\n", sc->sc_dev.dv_xname, phy, reg); }
int ANTARES_CHECK_DISABLE_INTERRUPTS(device_t dev) { struct rl_softc *sc = device_get_softc(dev); uint16_t status; status = CSR_READ_2(sc, RL_ISR); if (status == 0xffff) return 0; if (status != 0 && (status & RL_INTRS) == 0) { CSR_WRITE_2(sc, RL_ISR, status); return 0; } if ((status & RL_INTRS) == 0) return 0; CSR_WRITE_2(sc, RL_IMR, 0); return 1; }
int an_read_bap(struct an_softc *sc, int id, int off, void *buf, int len, int blen) { int error, cnt, cnt2; if (len == 0 || blen == 0) return 0; if (off == -1) off = sc->sc_bap_off; if (id != sc->sc_bap_id || off != sc->sc_bap_off) { if ((error = an_seek_bap(sc, id, off)) != 0) return EIO; } cnt = (blen + 1) / 2; CSR_READ_MULTI_STREAM_2(sc, AN_DATA0, (u_int16_t *)buf, cnt); for (cnt2 = (len + 1) / 2; cnt < cnt2; cnt++) (void) CSR_READ_2(sc, AN_DATA0); sc->sc_bap_off += cnt * 2; return 0; }
void an_linkstat_intr(struct an_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; u_int16_t status; status = CSR_READ_2(sc, AN_LINKSTAT); CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_LINKSTAT); DPRINTF(("an_linkstat_intr: status 0x%x\n", status)); if (status == AN_LINKSTAT_ASSOCIATED) { if (ic->ic_state != IEEE80211_S_RUN #ifndef IEEE80211_STA_ONLY || ic->ic_opmode == IEEE80211_M_IBSS #endif ) ieee80211_new_state(ic, IEEE80211_S_RUN, -1); } else { if (ic->ic_opmode == IEEE80211_M_STA) ieee80211_new_state(ic, IEEE80211_S_INIT, -1); } }
/* * The EEPROM is slow: give it time to come ready after issuing * it a command. */ int ste_eeprom_wait(struct ste_softc *sc) { int i; DELAY(1000); for (i = 0; i < 100; i++) { if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) DELAY(1000); else break; } if (i == 100) { printf("%s: eeprom failed to come ready\n", sc->sc_dev.dv_xname); return(1); } return(0); }