/**
* @INTERNAL
* Probe a SRIO interface and determine the number of ports
* connected to it. The SRIO interface should still be down
* after this call.
*
* @param interface Interface to probe
*
* @return Number of ports on the interface. Zero to disable.
*/
int __cvmx_helper_srio_probe(int interface)
{
cvmx_sriox_status_reg_t srio0_status_reg;
cvmx_sriox_status_reg_t srio1_status_reg;
if (!octeon_has_feature(OCTEON_FEATURE_SRIO))
return 0;
/* Read MIO_QLMX_CFG CSRs to find SRIO status. */
if (OCTEON_IS_MODEL(OCTEON_CN66XX))
{
int status = cvmx_qlm_get_status(0);
int srio_port = interface - 4;
switch(srio_port)
{
case 0: /* 1x4 lane */
if (status == 4)
return 2;
break;
case 2: /* 2x2 lane */
if (status == 5)
return 2;
break;
case 1: /* 4x1 long/short */
case 3: /* 4x1 long/short */
if (status == 6)
return 2;
break;
}
return 0;
}
srio0_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
srio1_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
if (srio0_status_reg.s.srio || srio1_status_reg.s.srio)
return 2;
else
return 0;
}
/**
* @INTERNAL
* Return the link state of an IPD/PKO port as returned by SRIO link status.
*
* @param ipd_port IPD/PKO port to query
*
* @return Link state
*/
cvmx_helper_link_info_t __cvmx_helper_srio_link_get(int ipd_port)
{
int interface = cvmx_helper_get_interface_num(ipd_port);
int srio_port = interface - 4;
cvmx_helper_link_info_t result;
cvmx_sriox_status_reg_t srio_status_reg;
cvmx_sriomaintx_port_0_err_stat_t sriomaintx_port_0_err_stat;
cvmx_sriomaintx_port_0_ctl_t sriomaintx_port_0_ctl;
cvmx_sriomaintx_port_0_ctl2_t sriomaintx_port_0_ctl2;
result.u64 = 0;
/* Make sure register access is allowed */
srio_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(srio_port));
if (!srio_status_reg.s.access)
return result;
/* Read the port link status */
if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_PORT_0_ERR_STAT(srio_port),
&sriomaintx_port_0_err_stat.u32))
return result;
/* Return if link is down */
if (!sriomaintx_port_0_err_stat.s.pt_ok)
return result;
/* Read the port link width and speed */
if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_PORT_0_CTL(srio_port),
&sriomaintx_port_0_ctl.u32))
return result;
if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_PORT_0_CTL2(srio_port),
&sriomaintx_port_0_ctl2.u32))
return result;
/* Link is up */
result.s.full_duplex = 1;
result.s.link_up = 1;
switch (sriomaintx_port_0_ctl2.s.sel_baud)
{
case 1:
result.s.speed = 1250;
break;
case 2:
result.s.speed = 2500;
break;
case 3:
result.s.speed = 3125;
break;
case 4:
result.s.speed = 5000;
break;
case 5:
result.s.speed = 6250;
break;
default:
result.s.speed = 0;
break;
}
switch (sriomaintx_port_0_ctl.s.it_width)
{
case 2: /* Four lanes */
result.s.speed += 40000;
break;
case 3: /* Two lanes */
result.s.speed += 20000;
break;
default: /* One lane */
result.s.speed += 10000;
break;
}
return result;
}
/**
* @INTERNAL
* Bringup and enable SRIO interface. After this call packet
* I/O should be fully functional. This is called with IPD
* enabled but PKO disabled.
*
* @param interface Interface to bring up
*
* @return Zero on success, negative on failure
*/
int __cvmx_helper_srio_enable(int interface)
{
int num_ports = cvmx_helper_ports_on_interface(interface);
int index;
cvmx_sriomaintx_core_enables_t sriomaintx_core_enables;
cvmx_sriox_imsg_ctrl_t sriox_imsg_ctrl;
cvmx_sriox_status_reg_t srio_status_reg;
cvmx_dpi_ctl_t dpi_ctl;
int srio_port = interface - 4;
/* All SRIO ports have a cvmx_srio_rx_message_header_t header
on them that must be skipped by IPD */
for (index=0; index<num_ports; index++)
{
cvmx_pip_prt_cfgx_t port_config;
cvmx_sriox_omsg_portx_t sriox_omsg_portx;
cvmx_sriox_omsg_sp_mrx_t sriox_omsg_sp_mrx;
cvmx_sriox_omsg_fmp_mrx_t sriox_omsg_fmp_mrx;
cvmx_sriox_omsg_nmp_mrx_t sriox_omsg_nmp_mrx;
int ipd_port = cvmx_helper_get_ipd_port(interface, index);
port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
/* Only change the skip if the user hasn't already set it */
if (!port_config.s.skip)
{
port_config.s.skip = sizeof(cvmx_srio_rx_message_header_t);
cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64);
}
/* Enable TX with PKO */
sriox_omsg_portx.u64 = cvmx_read_csr(CVMX_SRIOX_OMSG_PORTX(index, srio_port));
sriox_omsg_portx.s.port = (srio_port) * 2 + index;
sriox_omsg_portx.s.enable = 1;
cvmx_write_csr(CVMX_SRIOX_OMSG_PORTX(index, srio_port), sriox_omsg_portx.u64);
/* Allow OMSG controller to send regardless of the state of any other
controller. Allow messages to different IDs and MBOXes to go in
parallel */
sriox_omsg_sp_mrx.u64 = 0;
sriox_omsg_sp_mrx.s.xmbox_sp = 1;
sriox_omsg_sp_mrx.s.ctlr_sp = 1;
sriox_omsg_sp_mrx.s.ctlr_fmp = 1;
sriox_omsg_sp_mrx.s.ctlr_nmp = 1;
sriox_omsg_sp_mrx.s.id_sp = 1;
sriox_omsg_sp_mrx.s.id_fmp = 1;
sriox_omsg_sp_mrx.s.id_nmp = 1;
sriox_omsg_sp_mrx.s.mbox_sp = 1;
sriox_omsg_sp_mrx.s.mbox_fmp = 1;
sriox_omsg_sp_mrx.s.mbox_nmp = 1;
sriox_omsg_sp_mrx.s.all_psd = 1;
cvmx_write_csr(CVMX_SRIOX_OMSG_SP_MRX(index, srio_port), sriox_omsg_sp_mrx.u64);
/* Allow OMSG controller to send regardless of the state of any other
controller. Allow messages to different IDs and MBOXes to go in
parallel */
sriox_omsg_fmp_mrx.u64 = 0;
sriox_omsg_fmp_mrx.s.ctlr_sp = 1;
sriox_omsg_fmp_mrx.s.ctlr_fmp = 1;
sriox_omsg_fmp_mrx.s.ctlr_nmp = 1;
sriox_omsg_fmp_mrx.s.id_sp = 1;
sriox_omsg_fmp_mrx.s.id_fmp = 1;
sriox_omsg_fmp_mrx.s.id_nmp = 1;
sriox_omsg_fmp_mrx.s.mbox_sp = 1;
sriox_omsg_fmp_mrx.s.mbox_fmp = 1;
sriox_omsg_fmp_mrx.s.mbox_nmp = 1;
sriox_omsg_fmp_mrx.s.all_psd = 1;
cvmx_write_csr(CVMX_SRIOX_OMSG_FMP_MRX(index, srio_port), sriox_omsg_fmp_mrx.u64);
/* Once the first part of a message is accepted, always acept the rest
of the message */
sriox_omsg_nmp_mrx.u64 = 0;
sriox_omsg_nmp_mrx.s.all_sp = 1;
sriox_omsg_nmp_mrx.s.all_fmp = 1;
sriox_omsg_nmp_mrx.s.all_nmp = 1;
cvmx_write_csr(CVMX_SRIOX_OMSG_NMP_MRX(index, srio_port), sriox_omsg_nmp_mrx.u64);
}
/* Choose the receive controller based on the mailbox */
sriox_imsg_ctrl.u64 = cvmx_read_csr(CVMX_SRIOX_IMSG_CTRL(srio_port));
sriox_imsg_ctrl.s.prt_sel = 0;
sriox_imsg_ctrl.s.mbox = 0xa;
cvmx_write_csr(CVMX_SRIOX_IMSG_CTRL(srio_port), sriox_imsg_ctrl.u64);
/* DPI must be enabled for us to RX messages */
dpi_ctl.u64 = cvmx_read_csr(CVMX_DPI_CTL);
dpi_ctl.s.clk = 1;
dpi_ctl.s.en = 1;
cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64);
/* Make sure register access is allowed */
srio_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(srio_port));
if (!srio_status_reg.s.access)
return 0;
/* Enable RX */
if (!cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_CORE_ENABLES(srio_port), &sriomaintx_core_enables.u32))
{
sriomaintx_core_enables.s.imsg0 = 1;
sriomaintx_core_enables.s.imsg1 = 1;
cvmx_srio_config_write32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_CORE_ENABLES(srio_port), sriomaintx_core_enables.u32);
}
return 0;
}
/*
* Read QLM and return status based on CN66XX.
* @return Return 1 if QLM is SGMII
* 2 if QLM is XAUI
* 3 if QLM is PCIe gen2 / gen1
* 4 if QLM is SRIO 1x4 short / long
* 5 if QLM is SRIO 2x2 short / long
* 6 if QLM is SRIO 4x1 short / long
* 7 if QLM is PCIe 1x2 gen2 / gen1
* 8 if QLM is PCIe 2x1 gen2 / gen1
* 9 if QLM is ILK
* 10 if QLM is RXAUI
* -1 otherwise
*/
int cvmx_qlm_get_status(int qlm)
{
cvmx_mio_qlmx_cfg_t qlmx_cfg;
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
{
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
/* QLM is disabled when QLM SPD is 15. */
if (qlmx_cfg.s.qlm_spd == 15)
return -1;
switch (qlmx_cfg.s.qlm_cfg)
{
case 0: /* PCIE */
return 3;
case 1: /* ILK */
return 9;
case 2: /* SGMII */
return 1;
case 3: /* XAUI */
return 2;
case 7: /* RXAUI */
return 10;
default: return -1;
}
}
else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
{
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
/* QLM is disabled when QLM SPD is 15. */
if (qlmx_cfg.s.qlm_spd == 15)
return -1;
switch (qlmx_cfg.s.qlm_cfg)
{
case 0x9: /* SGMII */
return 1;
case 0xb: /* XAUI */
return 2;
case 0x0: /* PCIE gen2 */
case 0x8: /* PCIE gen2 (alias) */
case 0x2: /* PCIE gen1 */
case 0xa: /* PCIE gen1 (alias) */
return 3;
case 0x1: /* SRIO 1x4 short */
case 0x3: /* SRIO 1x4 long */
return 4;
case 0x4: /* SRIO 2x2 short */
case 0x6: /* SRIO 2x2 long */
return 5;
case 0x5: /* SRIO 4x1 short */
case 0x7: /* SRIO 4x1 long */
if (!OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_0))
return 6;
default:
return -1;
}
}
else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
{
cvmx_sriox_status_reg_t status_reg;
/* For now skip qlm2 */
if (qlm == 2)
{
cvmx_gmxx_inf_mode_t inf_mode;
inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(0));
if (inf_mode.s.speed == 15)
return -1;
else if(inf_mode.s.mode == 0)
return 1;
else
return 2;
}
status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(qlm));
if (status_reg.s.srio)
return 4;
else
return 3;
}
else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
{
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
/* QLM is disabled when QLM SPD is 15. */
if (qlmx_cfg.s.qlm_spd == 15)
return -1;
switch(qlm)
{
case 0:
switch (qlmx_cfg.s.qlm_cfg)
{
case 0: /* PCIe 1x4 gen2 / gen1 */
return 3;
case 2: /* SGMII */
return 1;
case 3: /* XAUI */
return 2;
default: return -1;
}
break;
case 1:
switch (qlmx_cfg.s.qlm_cfg)
{
case 0: /* PCIe 1x2 gen2 / gen1 */
return 7;
case 1: /* PCIe 2x1 gen2 / gen1 */
return 8;
default: return -1;
}
break;
case 2:
switch (qlmx_cfg.s.qlm_cfg)
{
case 2: /* SGMII */
return 1;
case 3: /* XAUI */
return 2;
default: return -1;
}
break;
}
}
else if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
{
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
/* QLM is disabled when QLM SPD is 15. */
if (qlmx_cfg.s.qlm_spd == 15)
return -1;
switch(qlm)
{
case 0:
if (qlmx_cfg.s.qlm_cfg == 2) /* SGMII */
return 1;
break;
case 1:
switch (qlmx_cfg.s.qlm_cfg)
{
case 0: /* PCIe 1x2 gen2 / gen1 */
return 7;
case 1: /* PCIe 2x1 gen2 / gen1 */
return 8;
default: return -1;
}
break;
}
}
return -1;
}
/**
* Get the speed (Gbaud) of the QLM in Mhz.
*
* @param qlm QLM to examine
*
* @return Speed in Mhz
*/
int cvmx_qlm_get_gbaud_mhz(int qlm)
{
if (OCTEON_IS_MODEL(OCTEON_CN63XX))
{
if (qlm == 2)
{
cvmx_gmxx_inf_mode_t inf_mode;
inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(0));
switch (inf_mode.s.speed)
{
case 0: return 5000; /* 5 Gbaud */
case 1: return 2500; /* 2.5 Gbaud */
case 2: return 2500; /* 2.5 Gbaud */
case 3: return 1250; /* 1.25 Gbaud */
case 4: return 1250; /* 1.25 Gbaud */
case 5: return 6250; /* 6.25 Gbaud */
case 6: return 5000; /* 5 Gbaud */
case 7: return 2500; /* 2.5 Gbaud */
case 8: return 3125; /* 3.125 Gbaud */
case 9: return 2500; /* 2.5 Gbaud */
case 10: return 1250; /* 1.25 Gbaud */
case 11: return 5000; /* 5 Gbaud */
case 12: return 6250; /* 6.25 Gbaud */
case 13: return 3750; /* 3.75 Gbaud */
case 14: return 3125; /* 3.125 Gbaud */
default: return 0; /* Disabled */
}
}
else
{
cvmx_sriox_status_reg_t status_reg;
status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(qlm));
if (status_reg.s.srio)
{
cvmx_sriomaintx_port_0_ctl2_t sriomaintx_port_0_ctl2;
sriomaintx_port_0_ctl2.u32 = cvmx_read_csr(CVMX_SRIOMAINTX_PORT_0_CTL2(qlm));
switch (sriomaintx_port_0_ctl2.s.sel_baud)
{
case 1: return 1250; /* 1.25 Gbaud */
case 2: return 2500; /* 2.5 Gbaud */
case 3: return 3125; /* 3.125 Gbaud */
case 4: return 5000; /* 5 Gbaud */
case 5: return 6250; /* 6.250 Gbaud */
default: return 0; /* Disabled */
}
}
else
{
cvmx_pciercx_cfg032_t pciercx_cfg032;
pciercx_cfg032.u32 = cvmx_read_csr(CVMX_PCIERCX_CFG032(qlm));
switch (pciercx_cfg032.s.ls)
{
case 1:
return 2500;
case 2:
return 5000;
case 4:
return 8000;
default:
{
cvmx_mio_rst_boot_t mio_rst_boot;
mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
if ((qlm == 0) && mio_rst_boot.s.qlm0_spd == 0xf)
return 0;
if ((qlm == 1) && mio_rst_boot.s.qlm1_spd == 0xf)
return 0;
return 5000; /* Best guess I can make */
}
}
}
}
}
else if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
{
cvmx_mio_qlmx_cfg_t qlm_cfg;
qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
switch (qlm_cfg.s.qlm_spd)
{
case 0: return 5000; /* 5 Gbaud */
case 1: return 2500; /* 2.5 Gbaud */
case 2: return 2500; /* 2.5 Gbaud */
case 3: return 1250; /* 1.25 Gbaud */
case 4: return 1250; /* 1.25 Gbaud */
case 5: return 6250; /* 6.25 Gbaud */
case 6: return 5000; /* 5 Gbaud */
case 7: return 2500; /* 2.5 Gbaud */
case 8: return 3125; /* 3.125 Gbaud */
case 9: return 2500; /* 2.5 Gbaud */
case 10: return 1250; /* 1.25 Gbaud */
case 11: return 5000; /* 5 Gbaud */
case 12: return 6250; /* 6.25 Gbaud */
case 13: return 3750; /* 3.75 Gbaud */
case 14: return 3125; /* 3.125 Gbaud */
default: return 0; /* Disabled */
}
}
return 0;
}
static enum cvmx_qlm_mode __cvmx_qlm_get_mode_cn6xxx(int qlm)
{
cvmx_mio_qlmx_cfg_t qlmx_cfg;
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
/* QLM is disabled when QLM SPD is 15. */
if (qlmx_cfg.s.qlm_spd == 15)
return CVMX_QLM_MODE_DISABLED;
switch (qlmx_cfg.s.qlm_cfg) {
case 0: /* PCIE */
return CVMX_QLM_MODE_PCIE;
case 1: /* ILK */
return CVMX_QLM_MODE_ILK;
case 2: /* SGMII */
return CVMX_QLM_MODE_SGMII;
case 3: /* XAUI */
return CVMX_QLM_MODE_XAUI;
case 7: /* RXAUI */
return CVMX_QLM_MODE_RXAUI;
default:
return CVMX_QLM_MODE_DISABLED;
}
} else if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
/* QLM is disabled when QLM SPD is 15. */
if (qlmx_cfg.s.qlm_spd == 15)
return CVMX_QLM_MODE_DISABLED;
switch (qlmx_cfg.s.qlm_cfg) {
case 0x9: /* SGMII */
return CVMX_QLM_MODE_SGMII;
case 0xb: /* XAUI */
return CVMX_QLM_MODE_XAUI;
case 0x0: /* PCIE gen2 */
case 0x8: /* PCIE gen2 (alias) */
case 0x2: /* PCIE gen1 */
case 0xa: /* PCIE gen1 (alias) */
return CVMX_QLM_MODE_PCIE;
case 0x1: /* SRIO 1x4 short */
case 0x3: /* SRIO 1x4 long */
return CVMX_QLM_MODE_SRIO_1X4;
case 0x4: /* SRIO 2x2 short */
case 0x6: /* SRIO 2x2 long */
return CVMX_QLM_MODE_SRIO_2X2;
case 0x5: /* SRIO 4x1 short */
case 0x7: /* SRIO 4x1 long */
if (!OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_0))
return CVMX_QLM_MODE_SRIO_4X1;
/* fallthrough */
default:
return CVMX_QLM_MODE_DISABLED;
}
} else if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
cvmx_sriox_status_reg_t status_reg;
/* For now skip qlm2 */
if (qlm == 2) {
cvmx_gmxx_inf_mode_t inf_mode;
inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(0));
if (inf_mode.s.speed == 15)
return CVMX_QLM_MODE_DISABLED;
else if (inf_mode.s.mode == 0)
return CVMX_QLM_MODE_SGMII;
else
return CVMX_QLM_MODE_XAUI;
}
status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(qlm));
if (status_reg.s.srio)
return CVMX_QLM_MODE_SRIO_1X4;
else
return CVMX_QLM_MODE_PCIE;
} else if (OCTEON_IS_MODEL(OCTEON_CN61XX)) {
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
/* QLM is disabled when QLM SPD is 15. */
if (qlmx_cfg.s.qlm_spd == 15)
return CVMX_QLM_MODE_DISABLED;
switch (qlm) {
case 0:
switch (qlmx_cfg.s.qlm_cfg) {
case 0: /* PCIe 1x4 gen2 / gen1 */
return CVMX_QLM_MODE_PCIE;
case 2: /* SGMII */
return CVMX_QLM_MODE_SGMII;
case 3: /* XAUI */
return CVMX_QLM_MODE_XAUI;
default:
return CVMX_QLM_MODE_DISABLED;
}
break;
case 1:
switch (qlmx_cfg.s.qlm_cfg) {
case 0: /* PCIe 1x2 gen2 / gen1 */
return CVMX_QLM_MODE_PCIE_1X2;
case 1: /* PCIe 2x1 gen2 / gen1 */
return CVMX_QLM_MODE_PCIE_2X1;
default:
return CVMX_QLM_MODE_DISABLED;
}
break;
case 2:
switch (qlmx_cfg.s.qlm_cfg) {
case 2: /* SGMII */
return CVMX_QLM_MODE_SGMII;
case 3: /* XAUI */
return CVMX_QLM_MODE_XAUI;
default:
return CVMX_QLM_MODE_DISABLED;
}
break;
}
} else if (OCTEON_IS_MODEL(OCTEON_CNF71XX)) {
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
/* QLM is disabled when QLM SPD is 15. */
if (qlmx_cfg.s.qlm_spd == 15)
return CVMX_QLM_MODE_DISABLED;
switch (qlm) {
case 0:
if (qlmx_cfg.s.qlm_cfg == 2) /* SGMII */
return CVMX_QLM_MODE_SGMII;
break;
case 1:
switch (qlmx_cfg.s.qlm_cfg) {
case 0: /* PCIe 1x2 gen2 / gen1 */
return CVMX_QLM_MODE_PCIE_1X2;
case 1: /* PCIe 2x1 gen2 / gen1 */
return CVMX_QLM_MODE_PCIE_2X1;
default:
return CVMX_QLM_MODE_DISABLED;
}
break;
}
}
return CVMX_QLM_MODE_DISABLED;
}
/**
* Get the speed (Gbaud) of the QLM in Mhz.
*
* @param qlm QLM to examine
*
* @return Speed in Mhz
*/
int cvmx_qlm_get_gbaud_mhz(int qlm)
{
if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
if (qlm == 2) {
cvmx_gmxx_inf_mode_t inf_mode;
inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(0));
switch (inf_mode.s.speed) {
case 0:
return 5000; /* 5 Gbaud */
case 1:
return 2500; /* 2.5 Gbaud */
case 2:
return 2500; /* 2.5 Gbaud */
case 3:
return 1250; /* 1.25 Gbaud */
case 4:
return 1250; /* 1.25 Gbaud */
case 5:
return 6250; /* 6.25 Gbaud */
case 6:
return 5000; /* 5 Gbaud */
case 7:
return 2500; /* 2.5 Gbaud */
case 8:
return 3125; /* 3.125 Gbaud */
case 9:
return 2500; /* 2.5 Gbaud */
case 10:
return 1250; /* 1.25 Gbaud */
case 11:
return 5000; /* 5 Gbaud */
case 12:
return 6250; /* 6.25 Gbaud */
case 13:
return 3750; /* 3.75 Gbaud */
case 14:
return 3125; /* 3.125 Gbaud */
default:
return 0; /* Disabled */
}
} else {
cvmx_sriox_status_reg_t status_reg;
status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(qlm));
if (status_reg.s.srio) {
cvmx_sriomaintx_port_0_ctl2_t sriomaintx_port_0_ctl2;
sriomaintx_port_0_ctl2.u32 = cvmx_read_csr(CVMX_SRIOMAINTX_PORT_0_CTL2(qlm));
switch (sriomaintx_port_0_ctl2.s.sel_baud) {
case 1:
return 1250; /* 1.25 Gbaud */
case 2:
return 2500; /* 2.5 Gbaud */
case 3:
return 3125; /* 3.125 Gbaud */
case 4:
return 5000; /* 5 Gbaud */
case 5:
return 6250; /* 6.250 Gbaud */
default:
return 0; /* Disabled */
}
} else {
cvmx_pciercx_cfg032_t pciercx_cfg032;
pciercx_cfg032.u32 = cvmx_read_csr(CVMX_PCIERCX_CFG032(qlm));
switch (pciercx_cfg032.s.ls) {
case 1:
return 2500;
case 2:
return 5000;
case 4:
return 8000;
default:
{
cvmx_mio_rst_boot_t mio_rst_boot;
mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
if ((qlm == 0) && mio_rst_boot.s.qlm0_spd == 0xf)
return 0;
if ((qlm == 1) && mio_rst_boot.s.qlm1_spd == 0xf)
return 0;
return 5000; /* Best guess I can make */
}
}
}
}
} else if (OCTEON_IS_OCTEON2()) {
cvmx_mio_qlmx_cfg_t qlm_cfg;
qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
switch (qlm_cfg.s.qlm_spd) {
case 0:
return 5000; /* 5 Gbaud */
case 1:
return 2500; /* 2.5 Gbaud */
case 2:
return 2500; /* 2.5 Gbaud */
case 3:
return 1250; /* 1.25 Gbaud */
case 4:
return 1250; /* 1.25 Gbaud */
case 5:
return 6250; /* 6.25 Gbaud */
case 6:
return 5000; /* 5 Gbaud */
case 7:
return 2500; /* 2.5 Gbaud */
case 8:
return 3125; /* 3.125 Gbaud */
case 9:
return 2500; /* 2.5 Gbaud */
case 10:
return 1250; /* 1.25 Gbaud */
case 11:
return 5000; /* 5 Gbaud */
case 12:
return 6250; /* 6.25 Gbaud */
case 13:
return 3750; /* 3.75 Gbaud */
case 14:
return 3125; /* 3.125 Gbaud */
default:
return 0; /* Disabled */
}
} else if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
cvmx_gserx_dlmx_mpll_multiplier_t mpll_multiplier;
uint64_t meas_refclock;
uint64_t freq;
/* Measure the reference clock */
meas_refclock = cvmx_qlm_measure_clock(qlm);
/* Multiply to get the final frequency */
mpll_multiplier.u64 = cvmx_read_csr(CVMX_GSERX_DLMX_MPLL_MULTIPLIER(qlm, 0));
freq = meas_refclock * mpll_multiplier.s.mpll_multiplier;
freq = (freq + 500000) / 1000000;
return freq;
}
return 0;
}
