static void __init_buffers(struct saa9730_priv_data *spd) { extern char cyg_io_atlas_2kbuffers[]; cyg_uint32 *bufp = (cyg_uint32 *)CYGARC_UNCACHED_ADDRESS((unsigned)cyg_io_atlas_2kbuffers); int i, j; for (i = 0; i < SAA9730_BUFFERS; i++) { for (j = 0; j < SAA9730_RXPKTS_PER_BUFFER; j++) { memset(bufp, 0, 2048); spd->rx_buffer[i][j] = bufp; bufp += SAA9730_PACKET_SIZE/sizeof(*bufp); } } for (i = 0; i < SAA9730_BUFFERS; i++) { for (j = 0; j < SAA9730_TXPKTS_PER_BUFFER; j++) { memset(bufp, 0, 2048); *bufp = CYG_CPU_TO_LE32(TX_EMPTY); spd->tx_buffer[i][j] = bufp; bufp += SAA9730_PACKET_SIZE/sizeof(*bufp); } } spd->next_rx_pindex = 0; spd->next_rx_bindex = 0; spd->next_tx_pindex = 0; spd->next_tx_bindex = 0; }
int flash_unlock_block(volatile unsigned long *block, int block_size, int blocks) { volatile unsigned long *ROM, *bp; unsigned long stat; int timeout = 5000000; unsigned char is_locked[MAX_FLASH_BLOCKS]; int i; FLASH_WRITE_ENABLE(); block = (volatile unsigned long *)CYGARC_UNCACHED_ADDRESS((unsigned long)block); ROM = (volatile unsigned long *)((unsigned long)block & FLASH_BASE_MASK); // Clear any error conditions ROM[0] = FLASH_Clear_Status; // Get current block lock state. This needs to access each block on // the device so currently locked blocks can be re-locked. bp = ROM; for (i = 0; i < (blocks/2); i++) { if (bp == block) { is_locked[i] = 0; } else { *bp = FLASH_Read_Query; is_locked[i] = bp[2]; } bp += block_size / sizeof(*bp); } // Clears all lock bits block[0] = FLASH_Clear_Locks; block[0] = FLASH_Clear_Locks_Confirm; // Confirmation timeout = 5000000; while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { if (--timeout == 0) break; } // Restore the lock state bp = ROM; for (i = 0; i < (blocks/2); i++) { if (is_locked[i]) { *bp = FLASH_Set_Lock; *bp = FLASH_Set_Lock_Confirm; // Confirmation timeout = 5000000; while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { if (--timeout == 0) break; } } bp += block_size / sizeof(*bp); } // Restore ROM to "normal" mode ROM[0] = FLASH_Reset; FLASH_WRITE_DISABLE(); return stat; }
int flash_program_buf(volatile unsigned long *addr, unsigned long *data, int len) { volatile unsigned long *ROM; unsigned long stat = 0; int timeout = 50000; FLASH_WRITE_ENABLE(); addr = (volatile unsigned long *)CYGARC_UNCACHED_ADDRESS((unsigned long)addr); ROM = (volatile unsigned long *)((unsigned long)addr & FLASH_BASE_MASK); // Clear any error conditions ROM[0] = FLASH_Clear_Status; while (len > 0) { ROM[0] = FLASH_Program; *addr = *data; timeout = 5000000; while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { if (--timeout == 0) { goto bad; } } if (stat & 0x007E007E) { break; } ROM[0] = FLASH_Reset; if (*addr++ != *data++) { stat = 0x99109910; break; } len -= 4; } // Restore ROM to "normal" mode bad: ROM[0] = FLASH_Reset; FLASH_WRITE_DISABLE(); return stat; }
int flash_erase_block(volatile unsigned long *block) { volatile unsigned long *ROM; unsigned long stat; int timeout = 50000; int len; FLASH_WRITE_ENABLE(); block = (volatile unsigned long *)CYGARC_UNCACHED_ADDRESS((unsigned long)block); ROM = (volatile unsigned long *)((unsigned long)block & FLASH_BASE_MASK); // Clear any error conditions ROM[0] = FLASH_Clear_Status; // Erase block ROM[0] = FLASH_Block_Erase; *block = FLASH_Confirm; timeout = 5000000; while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { if (--timeout == 0) break; } // Restore ROM to "normal" mode ROM[0] = FLASH_Reset; // If an error was reported, see if the block erased anyway if (stat & 0x007E007E) { len = FLASH_BLOCK_SIZE; while (len > 0) { if (*block++ != 0xFFFFFFFF) break; len -= sizeof(*block); } if (len == 0) stat = 0; } FLASH_WRITE_DISABLE(); return stat; }
static int ag7100_alloc_fifo(int ndesc, ag7100_desc_t **fifo) { int i; uint32_t size; unsigned char *p = NULL; size = sizeof(ag7100_desc_t) * ndesc; size += HAL_DCACHE_LINE_SIZE - 1; p = malloc(size); if (p == NULL) { printf("Cant allocate fifos\n"); return -1; } p = (unsigned char*)(((uint32_t)p + HAL_DCACHE_LINE_SIZE - 1) & ~(HAL_DCACHE_LINE_SIZE - 1)); p = (unsigned char*)(CYGARC_UNCACHED_ADDRESS((uint32_t)p)); for(i = 0; i < ndesc; i++) fifo[i] = (ag7100_desc_t *)p + i; return 0; }
#define IRS_Modem_Status 0x00 // FIFO control register #define FCR_ENABLE 0x01 #define FCR_CLEAR_RCVR 0x02 #define FCR_CLEAR_XMIT 0x04 //----------------------------------------------------------------------------- typedef struct { CYG_ADDRWORD base; cyg_int32 msec_timeout; int isr_vector; } channel_data_t; static channel_data_t channels[1] = { { .base = (CYGARC_UNCACHED_ADDRESS(AR7240_UART_BASE)), .msec_timeout = 1000, .isr_vector = 0}, }; //----------------------------------------------------------------------------- // Set the baud rate static void cyg_hal_plf_serial_set_baud(cyg_uint8* port, cyg_uint16 baud_divisor) { cyg_uint8 _lcr; HAL_READ_UINT32(port+SER_16550_LCR, _lcr); _lcr |= LCR_DL; HAL_WRITE_UINT32(port+SER_16550_LCR, _lcr);