static void
fxp_cardbus_setup(struct fxp_softc * sc)
{
struct fxp_cardbus_softc *csc = (struct fxp_cardbus_softc *)sc;
struct cardbus_softc *psc = device_private(device_parent(sc->sc_dev));
cardbus_chipset_tag_t cc = psc->sc_cc;
cardbus_function_tag_t cf = psc->sc_cf;
pcireg_t command;
cardbustag_t tag = cardbus_make_tag(cc, cf, csc->ct->ct_bus,
csc->ct->ct_func);
command = Cardbus_conf_read(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG);
if (csc->base0_reg) {
Cardbus_conf_write(csc->ct, tag,
CARDBUS_BASE0_REG, csc->base0_reg);
(cf->cardbus_ctrl) (cc, CARDBUS_MEM_ENABLE);
command |= CARDBUS_COMMAND_MEM_ENABLE |
CARDBUS_COMMAND_MASTER_ENABLE;
} else if (csc->base1_reg) {
Cardbus_conf_write(csc->ct, tag,
CARDBUS_BASE1_REG, csc->base1_reg);
(cf->cardbus_ctrl) (cc, CARDBUS_IO_ENABLE);
command |= (CARDBUS_COMMAND_IO_ENABLE |
CARDBUS_COMMAND_MASTER_ENABLE);
}
(cf->cardbus_ctrl) (cc, CARDBUS_BM_ENABLE);
/* enable the card */
Cardbus_conf_write(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG, command);
}
void
ral_cardbus_setup(struct ral_cardbus_softc *csc)
{
cardbus_devfunc_t ct = csc->sc_ct;
pcireg_t reg;
/* program the BAR */
Cardbus_conf_write(ct, csc->sc_tag, PCI_BAR0, csc->sc_bar_val);
/* enable the appropriate bits in the PCI CSR */
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
}
static void
uhci_cardbus_attach(device_t parent, device_t self,
void *aux)
{
struct uhci_cardbus_softc *sc = device_private(self);
struct cardbus_attach_args *ca = (struct cardbus_attach_args *)aux;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
pcitag_t tag = ca->ca_tag;
pcireg_t csr;
const char *vendor;
const char *devname = device_xname(self);
char devinfo[256];
usbd_status r;
sc->sc.sc_dev = self;
sc->sc.sc_bus.hci_private = sc;
pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class));
/* Map I/O registers */
if (Cardbus_mapreg_map(ct, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
&sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
printf("%s: can't map i/o space\n", devname);
return;
}
sc->sc_cc = cc;
sc->sc_cf = cf;
sc->sc_ct = ct;
sc->sc_tag = tag;
sc->sc.sc_bus.dmatag = ca->ca_dmat;
/* Enable the device. */
csr = Cardbus_conf_read(ct, tag, PCI_COMMAND_STATUS_REG);
Cardbus_conf_write(ct, tag, PCI_COMMAND_STATUS_REG,
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
/* Disable interrupts, so we don't get any spurious ones. */
bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0);
/* Map and establish the interrupt. */
sc->sc_ih = Cardbus_intr_establish(ct, IPL_USB, uhci_intr, sc);
if (sc->sc_ih == NULL) {
printf("%s: couldn't establish interrupt\n", devname);
return;
}
/* Set LEGSUP register to its default value. */
Cardbus_conf_write(ct, tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN);
switch(Cardbus_conf_read(ct, tag, PCI_USBREV) & PCI_USBREV_MASK) {
case PCI_USBREV_PRE_1_0:
sc->sc.sc_bus.usbrev = USBREV_PRE_1_0;
break;
case PCI_USBREV_1_0:
sc->sc.sc_bus.usbrev = USBREV_1_0;
break;
case PCI_USBREV_1_1:
sc->sc.sc_bus.usbrev = USBREV_1_1;
break;
default:
sc->sc.sc_bus.usbrev = USBREV_UNKNOWN;
break;
}
/* Figure out vendor for root hub descriptor. */
vendor = pci_findvendor(ca->ca_id);
sc->sc.sc_id_vendor = PCI_VENDOR(ca->ca_id);
if (vendor)
strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor));
else
snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
"vendor 0x%04x", PCI_VENDOR(ca->ca_id));
r = uhci_init(&sc->sc);
if (r != USBD_NORMAL_COMPLETION) {
printf("%s: init failed, error=%d\n", devname, r);
/* Avoid spurious interrupts. */
Cardbus_intr_disestablish(ct, sc->sc_ih);
sc->sc_ih = NULL;
return;
}
#if NEHCI_CARDBUS > 0
usb_cardbus_add(&sc->sc_cardbus, ca, self);
#endif
/* Attach usb device. */
sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
}
void
ahc_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct cardbus_attach_args *ca = aux;
struct ahc_cardbus_softc *csc = device_private(self);
struct ahc_softc *ahc = &csc->sc_ahc;
cardbus_devfunc_t ct = ca->ca_ct;
bus_space_tag_t bst;
bus_space_handle_t bsh;
pcireg_t reg;
u_int sxfrctl1 = 0;
u_char sblkctl;
ahc->sc_dev = self;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
printf(": Adaptec ADP-1480 SCSI\n");
/*
* Map the device.
*/
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
if (Cardbus_mapreg_map(csc->sc_ct, AHC_CARDBUS_MMBA,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&bst, &bsh, NULL, &csc->sc_size) == 0) {
csc->sc_bar = AHC_CARDBUS_MMBA;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
} else if (Cardbus_mapreg_map(csc->sc_ct, AHC_CARDBUS_IOBA,
PCI_MAPREG_TYPE_IO, 0, &bst, &bsh, NULL, &csc->sc_size) == 0) {
csc->sc_bar = AHC_CARDBUS_IOBA;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
} else {
csc->sc_bar = 0;
aprint_error("%s: unable to map device registers\n",
ahc_name(ahc));
return;
}
/* Enable the appropriate bits in the PCI CSR. */
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < 0x20) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (0x20 << PCI_LATTIMER_SHIFT);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
}
ahc_set_name(ahc, device_xname(ahc->sc_dev));
ahc->parent_dmat = ca->ca_dmat;
ahc->tag = bst;
ahc->bsh = bsh;
/*
* ADP-1480 is always an AIC-7860.
*/
ahc->chip = AHC_AIC7860 | AHC_PCI;
ahc->features = AHC_AIC7860_FE|AHC_REMOVABLE;
ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
if (PCI_REVISION(ca->ca_class) >= 1)
ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
if (ahc_softc_init(ahc) != 0)
return;
/*
* On all CardBus adapters, we allow SCB paging.
*/
ahc->flags = AHC_PAGESCBS;
ahc->channel = 'A';
ahc_intr_enable(ahc, FALSE);
ahc_reset(ahc);
/*
* Establish the interrupt.
*/
ahc->ih = Cardbus_intr_establish(ct, IPL_BIO, ahc_intr, ahc);
if (ahc->ih == NULL) {
aprint_error("%s: unable to establish interrupt\n",
ahc_name(ahc));
return;
}
ahc->seep_config = malloc(sizeof(*ahc->seep_config),
M_DEVBUF, M_NOWAIT);
if (ahc->seep_config == NULL)
return;
ahc_check_extport(ahc, &sxfrctl1);
/*
* Take the LED out of diagnostic mode.
*/
sblkctl = ahc_inb(ahc, SBLKCTL);
ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
/*
* I don't know where this is set in the SEEPROM or by the
* BIOS, so we default to 100%.
*/
ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
if (ahc->flags & AHC_USEDEFAULTS) {
int our_id;
/*
* Assume only one connector and always turn
* on termination.
*/
our_id = AHC_CARDBUS_DEFAULT_SCSI_ID;
sxfrctl1 = STPWEN;
ahc_outb(ahc, SCSICONF, our_id | ENSPCHK | RESET_SCSI);
ahc->our_id = our_id;
}
printf("%s: aic7860", ahc_name(ahc));
/*
* Record our termination setting for the
* generic initialization routine.
*/
if ((sxfrctl1 & STPWEN) != 0)
ahc->flags |= AHC_TERM_ENB_A;
if (ahc_init(ahc)) {
ahc_free(ahc);
return;
}
ahc_attach(ahc);
}
static void
njata_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct cardbus_attach_args *ca = aux;
struct njata32_cardbus_softc *csc = device_private(self);
struct njata32_softc *sc = &csc->sc_njata32;
const struct njata32_cardbus_product *prod;
cardbus_devfunc_t ct = ca->ca_ct;
pcireg_t reg;
int csr;
uint8_t latency = 0x20;
sc->sc_wdcdev.sc_atac.atac_dev = self;
if ((prod = njata_cardbus_lookup(ca)) == NULL)
panic("njata_cardbus_attach");
aprint_normal(": Workbit NinjaATA-32 IDE controller\n");
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
/*
* Map the device.
*/
csr = PCI_COMMAND_MASTER_ENABLE;
/*
* Map registers.
* Try memory map first, and then try I/O.
*/
if ((prod->p_flags & NJATA32_FL_IOMAP_ONLY) == 0 &&
Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_MEM,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&NJATA32_REGT(sc), &csc->sc_regmaph, NULL, &csc->sc_regmap_size)
== 0) {
if (bus_space_subregion(NJATA32_REGT(sc), csc->sc_regmaph,
NJATA32_MEMOFFSET_REG, NJATA32_REGSIZE, &NJATA32_REGH(sc))
!= 0) {
/* failed -- undo map and try I/O */
Cardbus_mapreg_unmap(csc->sc_ct,
NJATA32_CARDBUS_BASEADDR_MEM, NJATA32_REGT(sc),
csc->sc_regmaph, csc->sc_regmap_size);
goto try_io;
}
#ifdef NJATA32_DEBUG
aprint_normal("%s: memory space mapped, size %u\n",
NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
#endif
csr |= PCI_COMMAND_MEM_ENABLE;
sc->sc_flags = NJATA32_MEM_MAPPED;
} else {
try_io:
if (Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_IO,
PCI_MAPREG_TYPE_IO, 0, &NJATA32_REGT(sc),
&NJATA32_REGH(sc), NULL, &csc->sc_regmap_size) == 0) {
#ifdef NJATA32_DEBUG
aprint_normal("%s: io space mapped, size %u\n",
NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
#endif
csr |= PCI_COMMAND_IO_ENABLE;
sc->sc_flags = NJATA32_IO_MAPPED;
} else {
aprint_error("%s: unable to map device registers\n",
NJATA32NAME(sc));
return;
}
}
/* Enable the appropriate bits in the PCI CSR. */
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csr;
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < latency) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (latency << PCI_LATTIMER_SHIFT);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
}
sc->sc_dmat = ca->ca_dmat;
/*
* Establish the interrupt.
*/
sc->sc_ih = Cardbus_intr_establish(ct, IPL_BIO, njata32_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error("%s: unable to establish interrupt\n",
NJATA32NAME(sc));
return;
}
/* attach */
njata32_attach(sc);
}
int
com_cardbus_gofigure(struct cardbus_attach_args *ca,
struct com_cardbus_softc *csc)
{
int i, index = -1;
cardbusreg_t cis_ptr;
struct csdev *cp;
/* If this device is listed above, use the known values, */
cp = com_cardbus_find_csdev(ca);
if (cp != NULL) {
csc->cc_reg = cp->reg;
csc->cc_type = cp->type;
csc->cc_bug = cp->bug;
return (0);
}
cis_ptr = Cardbus_conf_read(csc->cc_ct, csc->cc_tag, CARDBUS_CIS_REG);
/* otherwise try to deduce which BAR and type to use from CIS. If
there is only one BAR, it must be the one we should use, if
there are more, we're out of luck. */
for (i = 0; i < 7; i++) {
/* ignore zero sized BARs */
if (ca->ca_cis.bar[i].size == 0)
continue;
/* ignore the CIS BAR */
if (CARDBUS_CIS_ASI_BAR(cis_ptr) ==
CARDBUS_CIS_ASI_BAR(ca->ca_cis.bar[i].flags))
continue;
if (index != -1)
goto multi_bar;
index = i;
}
if (index == -1) {
printf(": couldn't find any base address tuple\n");
return (1);
}
csc->cc_reg = CARDBUS_CIS_ASI_BAR(ca->ca_cis.bar[index].flags);
if ((ca->ca_cis.bar[index].flags & 0x10) == 0)
csc->cc_type = CARDBUS_MAPREG_TYPE_MEM;
else
csc->cc_type = CARDBUS_MAPREG_TYPE_IO;
return (0);
multi_bar:
printf(": there are more than one possible base\n");
printf("%s: address for this device, "
"please report the following information\n",
DEVNAME(csc));
printf("%s: vendor 0x%x product 0x%x\n", DEVNAME(csc),
CARDBUS_VENDOR(ca->ca_id), CARDBUS_PRODUCT(ca->ca_id));
for (i = 0; i < 7; i++) {
/* ignore zero sized BARs */
if (ca->ca_cis.bar[i].size == 0)
continue;
/* ignore the CIS BAR */
if (CARDBUS_CIS_ASI_BAR(cis_ptr) ==
CARDBUS_CIS_ASI_BAR(ca->ca_cis.bar[i].flags))
continue;
printf("%s: base address %x type %s size %x\n",
DEVNAME(csc), CARDBUS_CIS_ASI_BAR(ca->ca_cis.bar[i].flags),
(ca->ca_cis.bar[i].flags & 0x10) ? "i/o" : "mem",
ca->ca_cis.bar[i].size);
}
return (1);
}
void
ohci_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct ohci_cardbus_softc *sc = device_private(self);
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t csr;
char devinfo[256];
usbd_status r;
const char *vendor;
const char *devname = device_xname(self);
sc->sc.sc_dev = self;
sc->sc.sc_bus.hci_private = sc;
pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
printf(": %s (rev. 0x%02x)\n", devinfo,
PCI_REVISION(ca->ca_class));
/* Map I/O registers */
if (Cardbus_mapreg_map(ct, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
&sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
printf("%s: can't map mem space\n", devname);
return;
}
sc->sc_cc = cc;
sc->sc_cf = cf;
sc->sc_ct = ct;
sc->sc.sc_bus.dmatag = ca->ca_dmat;
/* Enable the device. */
csr = Cardbus_conf_read(ct, ca->ca_tag,
PCI_COMMAND_STATUS_REG);
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG,
csr | PCI_COMMAND_MASTER_ENABLE
| PCI_COMMAND_MEM_ENABLE);
/* Disable interrupts, so we don't can any spurious ones. */
bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
OHCI_ALL_INTRS);
sc->sc_ih = Cardbus_intr_establish(ct, IPL_USB, ohci_intr, sc);
if (sc->sc_ih == NULL) {
printf("%s: couldn't establish interrupt\n", devname);
return;
}
/* Figure out vendor for root hub descriptor. */
vendor = pci_findvendor(ca->ca_id);
sc->sc.sc_id_vendor = PCI_VENDOR(ca->ca_id);
if (vendor)
strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor));
else
snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
"vendor 0x%04x", PCI_VENDOR(ca->ca_id));
r = ohci_init(&sc->sc);
if (r != USBD_NORMAL_COMPLETION) {
printf("%s: init failed, error=%d\n", devname, r);
/* Avoid spurious interrupts. */
Cardbus_intr_disestablish(ct, sc->sc_ih);
sc->sc_ih = 0;
return;
}
#if NEHCI_CARDBUS > 0
usb_cardbus_add(&sc->sc_cardbus, ca, self);
#endif
if (!pmf_device_register1(self, ohci_suspend, ohci_resume,
ohci_shutdown))
aprint_error_dev(self, "couldn't establish power handler\n");
/* Attach usb device. */
sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
}
