static void Chip_USB_PllSetup(void) { /* No need to setup anything if PLL is already setup for the frequency */ if (Chip_Clock_GetClockInputHz(CLKIN_USBPLL) == usbPLLSetup.freq) return ; /* Setup default USB PLL state for a 480MHz output and attach */ Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup); /* enable USB PLL */ Chip_Clock_EnablePLL(CGU_USB_PLL); /* Wait for PLL lock */ while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED)) {} }
platform_result_t platform_spifi_init( const platform_spifi_t* spifi ) { uint32_t spifiBaseClockRate; uint32_t maxSpifiClock; /* if( spi_ptr->semaphore_is_inited == WICED_FALSE ) { host_rtos_init_semaphore( &spi_ptr->in_use_semaphore ); spi_ptr->semaphore_is_inited = WICED_TRUE; } else { host_rtos_get_semaphore( &spi_ptr->in_use_semaphore, NEVER_TIMEOUT, WICED_FALSE ); } */ /* Mux the port and pin to direct it to SPIFI */ platform_pin_set_alternate_function( &spifi->clock ); platform_pin_set_alternate_function( &spifi->miso ); platform_pin_set_alternate_function( &spifi->mosi ); platform_pin_set_alternate_function( &spifi->sio2 ); platform_pin_set_alternate_function( &spifi->sio3 ); platform_pin_set_alternate_function( &spifi->cs ); /* SPIFI base clock will be based on the main PLL rate and a divider */ spifiBaseClockRate = Chip_Clock_GetClockInputHz(CLKIN_MAINPLL); /* Setup SPIFI clock to run around 1Mhz. Use divider E for this, as it allows * higher divider values up to 256 maximum) */ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / 1000000) + 1)); Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); /* Initialize LPCSPIFILIB library, reset the interface */ spifiInit( ( uint32_t )spifi->spifi_base, true); /* register support for the family(s) we may want to work with */ spifiRegisterFamily( SPIFI_REG_FAMILY_MacronixMX25L ); /* Initialize and detect a device and get device context */ spifi_handle = spifiInitDevice( &lmem, sizeof(lmem), ( uint32_t ) spifi->spifi_base, SPIFLASH_BASE_ADDRESS ); /* Get some info needed for the application */ maxSpifiClock = spifiDevGetInfo(spifi_handle, SPIFI_INFO_MAXCLOCK); /* Setup SPIFI clock to at the maximum interface rate the detected device can use. This should be done after device init. */ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / maxSpifiClock) + 1)); /* start by unlocking the device */ if (spifiDevUnlockDevice(spifi_handle) != SPIFI_ERR_NONE) { return WICED_ERROR; } /* Enable quad. If not supported it will be ignored */ spifiDevSetOpts(spifi_handle, SPIFI_OPT_USE_QUAD, true); /* Enter memMode */ spifiDevSetMemMode(spifi_handle, true); /* Just a test */ maxSpifiClock = *( (uint32_t *)SPIFLASH_BASE_ADDRESS ); return spifi_handle == NULL ? WICED_ERROR : WICED_SUCCESS; }
static void RunExample(void) { uint32_t spifiBaseClockRate; uint32_t maxSpifiClock; uint16_t libVersion; SPIFI_HANDLE_T *pSpifi; /* Report the library version to start with */ libVersion = spifiGetLibVersion(); DEBUGOUT("\r\n\r\nSPIFI Lib Version %02d%02d\r\n", ((libVersion >> 8) & 0xff), (libVersion & 0xff)); /* set the blink rate to 1/2 second while testing */ test_suiteSetErrorBlinkRate(500); /* Setup SPIFI FLASH pin muxing (QUAD) */ Chip_SCU_SetPinMuxing(spifipinmuxing, sizeof(spifipinmuxing) / sizeof(PINMUX_GRP_T)); /* SPIFI base clock will be based on the main PLL rate and a divider */ spifiBaseClockRate = Chip_Clock_GetClockInputHz(CLKIN_MAINPLL); /* Setup SPIFI clock to run around 1Mhz. Use divider E for this, as it allows higher divider values up to 256 maximum) */ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / 1000000) + 1)); Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); DEBUGOUT("SPIFI clock rate %d\r\n", Chip_Clock_GetClockInputHz(CLKIN_IDIVE)); /* initialize and get a handle to the spifi lib */ pSpifi = initializeSpifi(); /* Get some info needed for the application */ maxSpifiClock = spifiDevGetInfo(pSpifi, SPIFI_INFO_MAXCLOCK); /* Get info */ DEBUGOUT("Device family = %s\r\n", spifiDevGetFamilyName(pSpifi)); DEBUGOUT("Capabilities = 0x%x\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_CAPS)); DEBUGOUT("Device size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_DEVSIZE)); DEBUGOUT("Max Clock Rate = %d\r\n", maxSpifiClock); DEBUGOUT("Erase blocks = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_BLOCKS)); DEBUGOUT("Erase block size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_BLOCKSIZE)); DEBUGOUT("Erase sub-blocks = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_SUBBLOCKS)); DEBUGOUT("Erase sub-blocksize = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_SUBBLOCKSIZE)); DEBUGOUT("Write page size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_PAGESIZE)); DEBUGOUT("Max single readsize = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_MAXREADSIZE)); DEBUGOUT("Current dev status = 0x%x\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_STATUS)); DEBUGOUT("Current options = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_OPTIONS)); /* Setup SPIFI clock to at the maximum interface rate the detected device can use. This should be done after device init. */ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / maxSpifiClock) + 1)); DEBUGOUT("SPIFI final Rate = %d\r\n", Chip_Clock_GetClockInputHz(CLKIN_IDIVE)); DEBUGOUT("\r\n"); /* Test the helper functions first */ test_suiteLibHelperBattery(pSpifi); /* Now test the erase functions first in block mode, then in address mode */ test_suiteLibEraseBattery(pSpifi, false); test_suiteLibEraseBattery(pSpifi, true); /* test data integrity */ test_suiteDataBattery(pSpifi, false, false); test_suiteDataBattery(pSpifi, true, false); test_suiteDataBattery(pSpifi, true, true); /* Done, de-init will enter memory mode */ spifiDevDeInit(pSpifi); /* Indicate success */ DEBUGOUT("Complete.\r\n"); test_suiteSetErrorBlinkRate(0); while (1) { __WFI(); } }
/** * @brief Main entry point * @return Nothing */ int main(void) { bool bool_status; uint32_t mainpll_freq, clkin_frq, dive_value, baseclk_frq, perclk_frq; CHIP_CGU_CLKIN_T clk_in, base_input; bool autoblocken; bool powerdn; int i; volatile int k = 1; SystemCoreClockUpdate(); Board_Init(); /* Print the Demo Information */ DEBUGOUT(menu); /* Main PLL should be locked, Check if Main PLL is locked */ DEBUGOUT("=========================================== \r\n"); DEBUGOUT("PLL functions \r\n"); DEBUGOUT("Main PLL : "); bool_status = Chip_Clock_MainPLLLocked(); if (bool_status == true) { DEBUGOUT("Locked\r\n"); } else { DEBUGOUT("Not Locked\r\n"); return 1; } /* Read Main PLL frequency in Hz */ mainpll_freq = Chip_Clock_GetMainPLLHz(); if (mainpll_freq == 0) { DEBUGOUT("Error in reading Main PLL frequency \r\n"); return 2; } DEBUGOUT("Main PLL Frequency in Hz : %d \r\n", mainpll_freq); DEBUGOUT("=========================================== \r\n"); DEBUGOUT("=========================================== \r\n"); DEBUGOUT("Clock Divider functions \r\n"); /* * Divider E divider is used for SPIFI, source is set to * Main PLL in SysInit code. * Read Divider E source & verify it */ clk_in = Chip_Clock_GetDividerSource(CLK_IDIV_E); if (clk_in != CLKIN_MAINPLL) { DEBUGOUT("Divider E source wrong %d \r\n", clk_in); return 3; } DEBUGOUT("Divider E source set to Main PLL \r\n"); /* * Divider E divider is used for SPIFI, divider value should be * between 3 and 5 set in SysInit code. * Read Divider E divider value & verify it */ dive_value = Chip_Clock_GetDividerDivisor(CLK_IDIV_E); if ( (dive_value < 3) && (dive_value > 5)) { DEBUGOUT("Divider E divider wrong %d \r\n", dive_value); return 4; } DEBUGOUT("Divider E divider value: %d \r\n", dive_value); DEBUGOUT("=========================================== \r\n"); /* * Read the frequencies of the input clock sources, * print it on UART prompt */ DEBUGOUT("=========================================== \r\n"); DEBUGOUT("Input clock frequencies \r\n"); DEBUGOUT("=========================================== \r\n"); for ( i = 0; i < (sizeof(clkin_info) / sizeof(CLKIN_NAME_T)); i++) { clkin_frq = Chip_Clock_GetClockInputHz(clkin_info[i].clk_in); DEBUGOUT(" %s Frequency : %d Hz \r\n", clkin_info[i].clkin_name, clkin_frq); } DEBUGOUT("=========================================== \r\n"); /* * Read the base clock settings & print on UART */ DEBUGOUT("=========================================== \r\n"); DEBUGOUT("Base Clock Setting Information \r\n"); DEBUGOUT("=========================================== \r\n"); for ( i = 0; i < (sizeof(baseclk_info) / sizeof(BASECLK_INFO_T)); i++) { /* Read Base clock info, only if base clock is enabled */ bool_status = Chip_Clock_IsBaseClockEnabled(baseclk_info[i].clock); if ( bool_status == true) { Chip_Clock_GetBaseClockOpts(baseclk_info[i].clock, &base_input, &autoblocken, &powerdn); /* Read Frequency of the base clock */ baseclk_frq = Chip_Clock_GetBaseClocktHz(baseclk_info[i].clock); /* Print details on UART */ DEBUGOUT("%s Input Clk: %d Base Clk Frq : %d Hz Auto block: %d Power down: %d \r\n", baseclk_info[i].clock_name, base_input, baseclk_frq, autoblocken, powerdn); } } DEBUGOUT("=========================================== \r\n"); /* * Read the peripheral clock rate & print on UART */ DEBUGOUT("=========================================== \r\n"); DEBUGOUT("Peripheral Clock Rates \r\n"); DEBUGOUT("=========================================== \r\n"); for ( i = 0; i < (sizeof(ccu_clk_info) / sizeof(CCUCLK_INFO_T)); i++) { /* Read Frequency of the peripheral clock */ perclk_frq = Chip_Clock_GetRate(ccu_clk_info[i].per_clk); /* Print the per clock only if it is enabled */ if (perclk_frq) { /* Print details on UART */ DEBUGOUT("%s Per Frq : %d Hz \r\n", ccu_clk_info[i].clock_name, perclk_frq); } } DEBUGOUT("=========================================== \r\n"); while (k) ; return 0; }