/* Setup Chip Core clock */ void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbase) { int i; if (clkin == CLKIN_CRYSTAL) { /* Switch main system clocking to crystal */ Chip_Clock_EnableCrystal(); } Chip_Clock_SetBaseClock(CLK_BASE_MX, clkin, true, false); if (core_freq > 110000000UL) { /* Setup PLL for 100MHz and switch main system clocking */ Chip_Clock_SetupMainPLLHz(clkin, CGU_IRC_FREQ, 110 * 1000000, 110 * 1000000); Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); } /* Setup PLL for maximum clock */ Chip_Clock_SetupMainPLLHz(clkin, OscRateIn, core_freq, core_freq); if (setbase) { /* Setup system base clocks and initial states. This won't enable and disable individual clocks, but sets up the base clock sources for each individual peripheral clock. */ for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); } } }
/* Set up and initialize clocking prior to call to main */ void Board_SetupClocking(void) { int i; Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true); /* Reset and enable 32Khz oscillator */ LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); /* Setup a divider E for main PLL clock switch SPIFI clock to that divider. Divide rate is based on CPU speed and speed of SPI FLASH part. */ #if (MAX_CLOCK_FREQ > 180000000) Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5); #else Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4); #endif Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); /* Setup system base clocks and initial states. This won't enable and disable individual clocks, but sets up the base clock sources for each individual peripheral clock. */ for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); } }
/* Setup system clocking */ STATIC void SystemSetupClocking(void) { int i; /* Switch main system clocking to crystal */ Chip_Clock_EnableCrystal(); Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false); /* Setup PLL for 100MHz and switch main system clocking */ Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000); Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); /* Setup PLL for maximum clock */ Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ); /* Setup system base clocks and initial states. This won't enable and disable individual clocks, but sets up the base clock sources for each individual peripheral clock. */ for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); } /* Reset and enable 32Khz oscillator */ LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); /* SPIFI pin setup is done prior to setting up system clocking */ for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) { Chip_SCU_PinMuxSet(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum, spifipinmuxing[i].modefunc); } /* Setup a divider E for main PLL clock switch SPIFI clock to that divider. Divide rate is based on CPU speed and speed of SPI FLASH part. */ #if (MAX_CLOCK_FREQ > 180000000) Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5); #else Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4); #endif Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); /* Attach main PLL clock to divider C with a divider of 2 */ Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2); /* Setup default USB PLL state for a 480MHz output and attach */ Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup); /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are chained to make a divide by 8 function. Connect the output of divider D to the USB1 base clock. */ Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4); Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2); Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true); /* Setup default audio PLL state for a FIXME output */ // Chip_Clock_SetupPLL(CGU_AUDIO_PLL, &audioPLLSetup); // FIXME }
/** * Post wake up initialisation function */ static void PMC_Post_Wakeup(uint8_t buffer) { int i; #ifdef BOARD_KEIL_MCB_18574357 /* Setup FLASH acceleration to target clock rate prior to clock switch */ Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ); #endif /* Reinitialise Clocks */ Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false); /* Setup PLL for 100MHz and switch main system clocking */ Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000); Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); /* Setup PLL for maximum clock */ Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ); /* Restore the base clock states */ for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); } /* Reset and enable 32Khz oscillator */ LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); /* Setup a divider E for main PLL clock switch SPIFI clock to that divider. Divide rate is based on CPU speed and speed of SPI FLASH part. */ #if (MAX_CLOCK_FREQ > 180000000) Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5); #else Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4); #endif Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); /* Attach main PLL clock to divider C with a divider of 2 */ Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2); /* Re-Initialize debug UART * � 115200bps * � 8 data bit * � No parity * � 1 stop bit * � No flow control */ DEBUGINIT(); #ifndef BOARD_NGX_XPLORER_18304330 /* SDRAM in NORMAL mode, only for Keil & Hitex boards */ LPC_EMC->DYNAMICCONTROL &= ~(1 << 2); while (LPC_EMC->STATUS & (1 << 2)) {} #endif }
/* Setup system clocking */ STATIC void SystemSetupClocking(void) { int i; /* Switch main system clocking to crystal */ Chip_Clock_EnableCrystal(); Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false); /* Setup PLL for 100MHz and switch main system clocking */ Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000); Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); /* Setup PLL for maximum clock */ Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ); /* Setup system base clocks and initial states. This won't enable and disable individual clocks, but sets up the base clock sources for each individual peripheral clock. */ for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); } /* Reset and enable 32Khz oscillator */ LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); /* SPIFI pin setup is done prior to setting up system clocking */ for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) { Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum, spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum); } /* Setup a divider E for main PLL clock switch SPIFI clock to that divider. Divide rate is based on CPU speed and speed of SPI FLASH part. */ #if (MAX_CLOCK_FREQ > 180000000) Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5); #else Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4); #endif Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); }
/** * Set IRC as source clock fo all the output clocks & power down * before going to 'Deep Sleep'/'Power Down'/'Deep Power Down' modes */ static void PMC_Pre_SleepPowerDown(void) { int i; #ifndef BOARD_NGX_XPLORER_18304330 /* SDRAM in self refresh mode only for Keil & Hitex boards */ LPC_EMC->DYNAMICCONTROL |= (1 << 2); while (!(LPC_EMC->STATUS & (1 << 2))) {} #endif /* Shutdown perpheral clocks with wake up enabled */ Chip_Clock_StartPowerDown(); /* Get state of individual base clocks & store them for restoring. * Sets up the IRC as base clock source */ for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { /* Get the Base clock settings */ Chip_Clock_GetBaseClockOpts(InitClkStates[i].clk, &InitClkStates[i].clkin, &InitClkStates[i].autoblock_enab, &InitClkStates[i].powerdn); /* Set IRC as clock input for all the base clocks */ Chip_Clock_SetBaseClock(InitClkStates[i].clk, CLKIN_IRC, InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); } /* Set IRC as clock source for SPIFI */ Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IRC, true, false); /* Set IRC as source clock for Core */ Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_IRC, true, false); #ifdef BOARD_KEIL_MCB_18574357 /* Set Flash acceleration */ Chip_CREG_SetFlashAcceleration(CRYSTAL_MAIN_FREQ_IN); #endif /* Power down the main PLL */ Chip_Clock_DisableMainPLL(); Chip_Clock_DisablePLL(CGU_USB_PLL); Chip_Clock_DisableCrystal(); }
/* Set up and initialize hardware prior to call to main */ void Chip_SystemInit(void) { int i; /* Switch main system clocking to IRC */ Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_IRC, true, false); /* Setup PLL for 100MHz and switch main system clocking */ Chip_Clock_SetupMainPLLHz(CLKIN_IRC, CGU_IRC_FREQ, 100 * 1000000, 100 * 1000000); Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); /* Setup PLL for maximum clock */ Chip_Clock_SetupMainPLLHz(CLKIN_IRC, CGU_IRC_FREQ, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ); /* Setup system base clocks and initial states. This won't enable and disable individual clocks, but sets up the base clock sources for each individual peripheral clock. */ for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); } }
void Chip_USB0_Init(void) { /* Set up USB PLL */ Chip_USB_PllSetup(); /* Setup USB0 base clock as clock out from USB PLL */ Chip_Clock_SetBaseClock( CLK_BASE_USB0, CLKIN_USBPLL, true, true); /* enable USB main clock */ Chip_Clock_EnableBaseClock(CLK_BASE_USB0); Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1); /* enable USB0 phy */ Chip_CREG_EnableUSB0Phy(); }
/** * @brief Main entry point * @return Nothing */ int main(void) { uint32_t SCT_FRQ; Board_Init(); /* Initialize SCT */ Chip_SCT_Init(LPC_SCT); LPC_SCU->SFSCLK[3] = SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC1; /* function 1; CGU clk out, pull up */ /* Attach IRC clock to divider B with a divider of 16 */ Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IRC, 16); /* Route divider B output to Clock output base clock and enable base out clock */ Chip_Clock_SetBaseClock(CLK_BASE_OUT, CLKIN_IDIVB, true, false); /* Configure SCT pins */ SCT_PinsConfigure(); SCT_FRQ = Chip_Clock_GetRate(CLK_MX_SCT); DEBUGOUT("SCT_FRQ: %d\r\n", SCT_FRQ); Chip_SCT_ControlSetClr(LPC_SCT, SCT_CTRL_CLRCTR_L | SCT_CTRL_HALT_L | SCT_CTRL_PRE_L(256 - 1) | SCT_CTRL_HALT_H | SCT_CTRL_CLRCTR_H | SCT_CTRL_PRE_H(256 - 1), ENABLE); /* Now use the FSM code to configure the state machine */ sct_fsm_init(); /* initialize random seed: */ srand(0x5EED); /* 12000000 / 256 / 16 = 2929 Hz * 65535 / 2929 =~ 22 */ /* generate a random delay from 1 to 22 seconds */ delay = (rand() % 22 + 1) * 2929; NVIC_ClearPendingIRQ(SCT_IRQn); NVIC_EnableIRQ(SCT_IRQn); /* Start the SCT */ Chip_SCT_ControlSetClr(LPC_SCT, SCT_CTRL_STOP_L | SCT_CTRL_HALT_L | SCT_CTRL_STOP_H | SCT_CTRL_HALT_H, DISABLE); while (1) { __WFI(); } }
void Chip_USB1_Init(void) { /* Setup and enable the PLL */ Chip_USB_PllSetup(); /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are chained to make a divide by 8 function. Connect the output of divider D to the USB1 base clock. */ Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4); Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2); Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true); /* enable USB main clock */ Chip_Clock_EnableBaseClock(CLK_BASE_USB1); Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1); /* enable USB1_DP and USB1_DN on chip FS phy.*/ LPC_SCU->SFSUSB = 0x12; }
/* Board Audio initialization */ void Board_Audio_Init(LPC_I2S_T *pI2S, int micIn) { if (pI2S == LPC_I2S0) { /* TODO :Add pin mux for I2S0 later */ } else if (pI2S == LPC_I2S1) { Chip_SCU_PinMuxSet (0x1, 19, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* I2S1_TX_SCK */ Chip_SCU_PinMuxSet (0x0, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* I2S1_TX_SDA */ Chip_SCU_PinMuxSet (0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC6)); /* I2S1_RX_SDA */ Chip_SCU_PinMuxSet (0x0, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* I2S1_TX_WS */ Chip_SCU_ClockPinMuxSet(0,(SCU_MODE_FUNC1|SCU_MODE_INACT)); /* Setup base clock for CLKOUT */ Chip_Clock_SetBaseClock(CLK_BASE_OUT, CLKIN_CRYSTAL, false, false); } else { /* It is a BUG catch it */ while(1); } /* Init WM8904 CODEC */ while (Board_Audio_CodecInit(micIn) != SUCCESS) {} }
int main(void) { CCAN_MSG_OBJ_T send_obj; SystemCoreClockUpdate(); Board_Init(); set_pinmux(); DEBUGOUT(WelcomeMenu); /* Set CCAN peripheral clock under 100Mhz for working stable */ Chip_Clock_SetBaseClock(CLK_BASE_APB3, CLKIN_IDIVC, true, false); Chip_CCAN_Init(LPC_C_CAN0); Chip_CCAN_SetBitRate(LPC_C_CAN0, 500000); Chip_CCAN_EnableInt(LPC_C_CAN0, (CCAN_CTRL_IE | CCAN_CTRL_SIE | CCAN_CTRL_EIE)); send_obj.id = CCAN_TX_MSG_ID; send_obj.dlc = 4; send_obj.data[0] = 'A'; send_obj.data[1] = 'B'; send_obj.data[2] = 'C'; send_obj.data[3] = 'D'; Chip_CCAN_Send(LPC_C_CAN0, CCAN_MSG_IF1, false, &send_obj); Chip_CCAN_ClearStatus(LPC_C_CAN0, CCAN_STAT_TXOK); send_obj.id = CCAN_TX_MSG_REMOTE_ID; send_obj.data[0] = 'E'; send_obj.data[1] = 'F'; send_obj.data[2] = 'G'; send_obj.data[3] = 'H'; Chip_CCAN_Send(LPC_C_CAN0, CCAN_MSG_IF1, true, &send_obj); Chip_CCAN_ClearStatus(LPC_C_CAN0, CCAN_STAT_TXOK); Chip_CCAN_AddReceiveID(LPC_C_CAN0, CCAN_MSG_IF1, CCAN_RX_MSG_ID); NVIC_EnableIRQ(C_CAN0_IRQn); while (1) {} }
platform_result_t platform_spifi_init( const platform_spifi_t* spifi ) { uint32_t spifiBaseClockRate; uint32_t maxSpifiClock; /* if( spi_ptr->semaphore_is_inited == WICED_FALSE ) { host_rtos_init_semaphore( &spi_ptr->in_use_semaphore ); spi_ptr->semaphore_is_inited = WICED_TRUE; } else { host_rtos_get_semaphore( &spi_ptr->in_use_semaphore, NEVER_TIMEOUT, WICED_FALSE ); } */ /* Mux the port and pin to direct it to SPIFI */ platform_pin_set_alternate_function( &spifi->clock ); platform_pin_set_alternate_function( &spifi->miso ); platform_pin_set_alternate_function( &spifi->mosi ); platform_pin_set_alternate_function( &spifi->sio2 ); platform_pin_set_alternate_function( &spifi->sio3 ); platform_pin_set_alternate_function( &spifi->cs ); /* SPIFI base clock will be based on the main PLL rate and a divider */ spifiBaseClockRate = Chip_Clock_GetClockInputHz(CLKIN_MAINPLL); /* Setup SPIFI clock to run around 1Mhz. Use divider E for this, as it allows * higher divider values up to 256 maximum) */ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / 1000000) + 1)); Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); /* Initialize LPCSPIFILIB library, reset the interface */ spifiInit( ( uint32_t )spifi->spifi_base, true); /* register support for the family(s) we may want to work with */ spifiRegisterFamily( SPIFI_REG_FAMILY_MacronixMX25L ); /* Initialize and detect a device and get device context */ spifi_handle = spifiInitDevice( &lmem, sizeof(lmem), ( uint32_t ) spifi->spifi_base, SPIFLASH_BASE_ADDRESS ); /* Get some info needed for the application */ maxSpifiClock = spifiDevGetInfo(spifi_handle, SPIFI_INFO_MAXCLOCK); /* Setup SPIFI clock to at the maximum interface rate the detected device can use. This should be done after device init. */ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / maxSpifiClock) + 1)); /* start by unlocking the device */ if (spifiDevUnlockDevice(spifi_handle) != SPIFI_ERR_NONE) { return WICED_ERROR; } /* Enable quad. If not supported it will be ignored */ spifiDevSetOpts(spifi_handle, SPIFI_OPT_USE_QUAD, true); /* Enter memMode */ spifiDevSetMemMode(spifi_handle, true); /* Just a test */ maxSpifiClock = *( (uint32_t *)SPIFLASH_BASE_ADDRESS ); return spifi_handle == NULL ? WICED_ERROR : WICED_SUCCESS; }
static void RunExample(void) { uint32_t spifiBaseClockRate; uint32_t maxSpifiClock; uint16_t libVersion; SPIFI_HANDLE_T *pSpifi; /* Report the library version to start with */ libVersion = spifiGetLibVersion(); DEBUGOUT("\r\n\r\nSPIFI Lib Version %02d%02d\r\n", ((libVersion >> 8) & 0xff), (libVersion & 0xff)); /* set the blink rate to 1/2 second while testing */ test_suiteSetErrorBlinkRate(500); /* Setup SPIFI FLASH pin muxing (QUAD) */ Chip_SCU_SetPinMuxing(spifipinmuxing, sizeof(spifipinmuxing) / sizeof(PINMUX_GRP_T)); /* SPIFI base clock will be based on the main PLL rate and a divider */ spifiBaseClockRate = Chip_Clock_GetClockInputHz(CLKIN_MAINPLL); /* Setup SPIFI clock to run around 1Mhz. Use divider E for this, as it allows higher divider values up to 256 maximum) */ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / 1000000) + 1)); Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); DEBUGOUT("SPIFI clock rate %d\r\n", Chip_Clock_GetClockInputHz(CLKIN_IDIVE)); /* initialize and get a handle to the spifi lib */ pSpifi = initializeSpifi(); /* Get some info needed for the application */ maxSpifiClock = spifiDevGetInfo(pSpifi, SPIFI_INFO_MAXCLOCK); /* Get info */ DEBUGOUT("Device family = %s\r\n", spifiDevGetFamilyName(pSpifi)); DEBUGOUT("Capabilities = 0x%x\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_CAPS)); DEBUGOUT("Device size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_DEVSIZE)); DEBUGOUT("Max Clock Rate = %d\r\n", maxSpifiClock); DEBUGOUT("Erase blocks = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_BLOCKS)); DEBUGOUT("Erase block size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_BLOCKSIZE)); DEBUGOUT("Erase sub-blocks = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_SUBBLOCKS)); DEBUGOUT("Erase sub-blocksize = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_SUBBLOCKSIZE)); DEBUGOUT("Write page size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_PAGESIZE)); DEBUGOUT("Max single readsize = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_MAXREADSIZE)); DEBUGOUT("Current dev status = 0x%x\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_STATUS)); DEBUGOUT("Current options = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_OPTIONS)); /* Setup SPIFI clock to at the maximum interface rate the detected device can use. This should be done after device init. */ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / maxSpifiClock) + 1)); DEBUGOUT("SPIFI final Rate = %d\r\n", Chip_Clock_GetClockInputHz(CLKIN_IDIVE)); DEBUGOUT("\r\n"); /* Test the helper functions first */ test_suiteLibHelperBattery(pSpifi); /* Now test the erase functions first in block mode, then in address mode */ test_suiteLibEraseBattery(pSpifi, false); test_suiteLibEraseBattery(pSpifi, true); /* test data integrity */ test_suiteDataBattery(pSpifi, false, false); test_suiteDataBattery(pSpifi, true, false); test_suiteDataBattery(pSpifi, true, true); /* Done, de-init will enter memory mode */ spifiDevDeInit(pSpifi); /* Indicate success */ DEBUGOUT("Complete.\r\n"); test_suiteSetErrorBlinkRate(0); while (1) { __WFI(); } }