/* Setup Chip Core clock */
void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbase)
{
int i;
if (clkin == CLKIN_CRYSTAL) {
/* Switch main system clocking to crystal */
Chip_Clock_EnableCrystal();
}
Chip_Clock_SetBaseClock(CLK_BASE_MX, clkin, true, false);
if (core_freq > 110000000UL) {
/* Setup PLL for 100MHz and switch main system clocking */
Chip_Clock_SetupMainPLLHz(clkin, CGU_IRC_FREQ, 110 * 1000000, 110 * 1000000);
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
}
/* Setup PLL for maximum clock */
Chip_Clock_SetupMainPLLHz(clkin, OscRateIn, core_freq, core_freq);
if (setbase) {
/* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}
}
}
/* Setup system clocking */
STATIC void SystemSetupClocking(void)
{
int i;
/* Switch main system clocking to crystal */
Chip_Clock_EnableCrystal();
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
/* Setup PLL for 100MHz and switch main system clocking */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
/* Setup PLL for maximum clock */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
/* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}
/* Reset and enable 32Khz oscillator */
LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
/* SPIFI pin setup is done prior to setting up system clocking */
for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
Chip_SCU_PinMuxSet(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
spifipinmuxing[i].modefunc);
}
/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
Divide rate is based on CPU speed and speed of SPI FLASH part. */
#if (MAX_CLOCK_FREQ > 180000000)
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
#else
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
#endif
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
/* Attach main PLL clock to divider C with a divider of 2 */
Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
/* Setup default USB PLL state for a 480MHz output and attach */
Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);
/* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
chained to make a divide by 8 function. Connect the output of
divider D to the USB1 base clock. */
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);
Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);
Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
/* Setup default audio PLL state for a FIXME output */
// Chip_Clock_SetupPLL(CGU_AUDIO_PLL, &audioPLLSetup); // FIXME
}
/**
* Post wake up initialisation function
*/
static void PMC_Post_Wakeup(uint8_t buffer)
{
int i;
#ifdef BOARD_KEIL_MCB_18574357
/* Setup FLASH acceleration to target clock rate prior to clock switch */
Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ);
#endif
/* Reinitialise Clocks */
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
/* Setup PLL for 100MHz and switch main system clocking */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
/* Setup PLL for maximum clock */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
/* Restore the base clock states */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}
/* Reset and enable 32Khz oscillator */
LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
Divide rate is based on CPU speed and speed of SPI FLASH part. */
#if (MAX_CLOCK_FREQ > 180000000)
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
#else
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
#endif
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
/* Attach main PLL clock to divider C with a divider of 2 */
Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
/* Re-Initialize debug UART
* � 115200bps
* � 8 data bit
* � No parity
* � 1 stop bit
* � No flow control
*/
DEBUGINIT();
#ifndef BOARD_NGX_XPLORER_18304330
/* SDRAM in NORMAL mode, only for Keil & Hitex boards */
LPC_EMC->DYNAMICCONTROL &= ~(1 << 2);
while (LPC_EMC->STATUS & (1 << 2)) {}
#endif
}
/* Setup system clocking */
STATIC void SystemSetupClocking(void)
{
int i;
/* Switch main system clocking to crystal */
Chip_Clock_EnableCrystal();
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
/* Setup PLL for 100MHz and switch main system clocking */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
/* Setup PLL for maximum clock */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
/* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}
/* Reset and enable 32Khz oscillator */
LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
/* SPIFI pin setup is done prior to setting up system clocking */
for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
}
/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
Divide rate is based on CPU speed and speed of SPI FLASH part. */
#if (MAX_CLOCK_FREQ > 180000000)
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
#else
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
#endif
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
}
/* Set up and initialize hardware prior to call to main */
void Chip_SystemInit(void)
{
int i;
/* Switch main system clocking to IRC */
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_IRC, true, false);
/* Setup PLL for 100MHz and switch main system clocking */
Chip_Clock_SetupMainPLLHz(CLKIN_IRC, CGU_IRC_FREQ, 100 * 1000000, 100 * 1000000);
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
/* Setup PLL for maximum clock */
Chip_Clock_SetupMainPLLHz(CLKIN_IRC, CGU_IRC_FREQ, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
/* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}
}
