/* Basic Ethernet interface initialization */ void Chip_ENET_Init(void) { LPC_CREG->CREG6 &= ~0x7; /* Enable ethernet clock */ Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1); /* PHY TX/RX base clock routing is setup as part of SystemInit() */ #if defined(USE_RMII) LPC_CREG->CREG6 |= 0x4; #endif /* Reset ethernet and wait for reset to complete */ Chip_RGU_TriggerReset(RGU_ETHERNET_RST); while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {} /* Reset ethernet peripheral */ Chip_ENET_Reset(); /* Setup MII link divider to /102 and PHY address 1 */ Chip_ENET_Setup_MII(4, 1); IP_ENET_Init(LPC_ETHERNET); }
STATIC INLINE void reset(LPC_ENET_T *pENET) { Chip_RGU_TriggerReset(RGU_ETHERNET_RST); while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {} /* Reset ethernet peripheral */ Chip_ENET_Reset(pENET); }
static inline void resetENET(LPC_ENET_T *pENET) { volatile uint32_t i; #if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) Chip_SYSCTL_PeriphReset(SYSCTL_RESET_ENET); #endif /* Reset ethernet peripheral */ Chip_ENET_Reset(pENET); for (i = 0; i < 100; i++) {} }