extern int32_t ciaaDriverUart_ioctl(ciaaDevices_deviceType const * const device, int32_t const request, void * param)
{
int32_t ret = -1;
if((device == ciaaDriverUartConst.devices[0]) ||
(device == ciaaDriverUartConst.devices[1]) ||
(device == ciaaDriverUartConst.devices[2]) )
{
switch(request)
{
case ciaaPOSIX_IOCTL_STARTTX:
/* disable THRE irq (TX) */
Chip_UART_IntDisable((LPC_USART_T *)device->loLayer, UART_IER_THREINT);
/* this one calls write */
ciaaDriverUart_txConfirmation(device);
/* enable THRE irq (TX) */
Chip_UART_IntEnable((LPC_USART_T *)device->loLayer, UART_IER_THREINT);
ret = 0;
break;
case ciaaPOSIX_IOCTL_SET_BAUDRATE:
ret = Chip_UART_SetBaud((LPC_USART_T *)device->loLayer, (int32_t)param);
break;
case ciaaPOSIX_IOCTL_SET_FIFO_TRIGGER_LEVEL:
Chip_UART_SetupFIFOS((LPC_USART_T *)device->loLayer, UART_FCR_FIFO_EN | UART_FCR_TX_RS | UART_FCR_RX_RS | (int32_t)param);
break;
case ciaaPOSIX_IOCTL_SET_ENABLE_TX_INTERRUPT:
if((bool)(intptr_t)param == false)
{
/* disable THRE irq (TX) */
Chip_UART_IntDisable((LPC_USART_T *)device->loLayer, UART_IER_THREINT);
}
else
{
/* enable THRE irq (TX) */
Chip_UART_IntEnable((LPC_USART_T *)device->loLayer, UART_IER_THREINT);
}
break;
case ciaaPOSIX_IOCTL_SET_ENABLE_RX_INTERRUPT:
if((bool)(intptr_t)param == false)
{
/* disable RBR irq (RX) */
Chip_UART_IntDisable((LPC_USART_T *)device->loLayer, UART_IER_RBRINT);
}
else
{
/* enable RBR irq (RX) */
Chip_UART_IntEnable((LPC_USART_T *)device->loLayer, UART_IER_RBRINT);
}
break;
}
}
return ret;
}
/* DeInitialize Interrupt for UART */
static void App_Interrupt_DeInit(void)
{
/* Disable UART Rx & line status interrupts */
Chip_UART_IntDisable(LPC_UART, (UART_IER_RBRINT | UART_IER_RLSINT));
/* Disable Interrupt for UART channel */
NVIC_DisableIRQ(UARTx_IRQn);
}
int skynetbase_gps_init(void) {
DBG("begin init GPS...\n");
NVIC_DisableIRQ(GPS_IRQn);
Chip_UART_IntDisable(GPS_UART, (UART_IER_RBRINT | UART_IER_RLSINT));
Chip_UART_Init(GPS_UART);
Chip_UART_SetBaud(GPS_UART, 9600);
Chip_UART_ConfigData(GPS_UART, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT));
Chip_UART_SetupFIFOS(GPS_UART, (UART_FCR_FIFO_EN | UART_FCR_TRG_LEV2));
Chip_UART_TXEnable(GPS_UART);
// Before using the ring buffers, initialize them using the ring buffer init function
RingBuffer_Init(&rxring, rxbuff, 1, UART_RRB_SIZE);
RingBuffer_Init(&txring, txbuff, 1, UART_SRB_SIZE);
// Reset and enable FIFOs, FIFO trigger level 3 (14 chars)
Chip_UART_SetupFIFOS(GPS_UART, (UART_FCR_FIFO_EN | UART_FCR_RX_RS |
UART_FCR_TX_RS | UART_FCR_TRG_LEV3));
/* Enable receive data and line status interrupt */
Chip_UART_IntEnable(GPS_UART, (UART_IER_RBRINT | UART_IER_RLSINT));
/* preemption = 1, sub-priority = 1 */
NVIC_SetPriority(GPS_IRQn, 1);
NVIC_EnableIRQ(GPS_IRQn);
DBG("GPS up.\n");
skynetbase_gps_config("$PUBX,40,GLL,0,0,0,0*5C\r\n");
msDelayActive(250);
skynetbase_gps_config("$PUBX,40,ZDA,0,0,0,0*44\r\n");
msDelayActive(250);
skynetbase_gps_config("$PUBX,40,VTG,0,0,0,0*5E\r\n");
msDelayActive(250);
skynetbase_gps_config("$PUBX,40,GSV,0,0,0,0*59\r\n");
msDelayActive(250);
skynetbase_gps_config("$PUBX,40,RMC,0,0,0,0*47\r\n");
msDelayActive(250);
skynetbase_gps_config("$PUBX,40,GSA,0,0,0,0*4E\r\n");
msDelayActive(250);
skynetbase_gps_config("$PUBX,40,GGA,0,0,0,0*5A\r\n");
msDelayActive(250);
DBG("GPS configured.\n");
// TODO
return 1;
}
/* UART receive/transmit interrupt handler for ring buffers */
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB)
{
/* Handle transmit interrupt if enabled */
if (pUART->IER & UART_IER_THREINT) {
Chip_UART_TXIntHandlerRB(pUART, pTXRB);
/* Disable transmit interrupt if the ring buffer is empty */
if (RingBuffer_IsEmpty(pTXRB)) {
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
}
}
/* Handle receive interrupt */
Chip_UART_RXIntHandlerRB(pUART, pRXRB);
}
/* UART receive/transmit interrupt handler for ring buffers */
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB)
{
/* Handle transmit interrupt if enabled */
if ((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0) {
Chip_UART_TXIntHandlerRB(pUART, pTXRB);
/* Disable transmit interrupt if the ring buffer is empty */
if (RingBuffer_IsEmpty(pTXRB)) {
Chip_UART_IntDisable(pUART, UART_INTEN_TXRDY);
}
}
/* Handle receive interrupt */
Chip_UART_RXIntHandlerRB(pUART, pRXRB);
}
/* Populate a transmit ring buffer and start UART transmit */
uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes)
{
uint32_t ret;
uint8_t *p8 = (uint8_t *) data;
/* Don't let UART transmit ring buffer change in the UART IRQ handler */
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
/* Move as much data as possible into transmit ring buffer */
ret = RingBuffer_InsertMult(pRB, p8, bytes);
Chip_UART_TXIntHandlerRB(pUART, pRB);
/* Add additional data to transmit ring buffer if possible */
ret += RingBuffer_InsertMult(pRB, (p8 + ret), (bytes - ret));
/* Enable UART transmit interrupt */
Chip_UART_IntEnable(pUART, UART_IER_THREINT);
return ret;
}
/**
* @brief UART interrupt handler sub-routine
* @return Nothing
*/
void UART_IRQHandler(void)
{
uint32_t count = 0;
/* Handle transmit interrupt if enabled */
if (LPC_USART->IER & UART_IER_THREINT) {
if (g_uCOM.txBuf_count > 0) {
count = Chip_UART_Send(LPC_USART, &g_uCOM.txBuf[g_uCOM.txBuf_uartIndex], g_uCOM.txBuf_count);
g_uCOM.txBuf_count -= count;
g_uCOM.txBuf_uartIndex += count;
}
/* If usbRxBuf empty check if any packet pending USB EP RAM */
if (g_uCOM.txBuf_count < 1) {
if (g_uCOM.usbRxPending > 0) {
g_uCOM.usbRxPending--;
g_uCOM.txBuf_count = USBD_API->hw->ReadEP(g_uCOM.hUsb, USB_CDC_OUT_EP, g_uCOM.txBuf);
g_uCOM.txBuf_uartIndex = 0;
}
else {
/* all data transmitted on UART disable UART_IER_THREINT */
Chip_UART_IntDisable(LPC_USART, UART_IER_THREINT);
}
}
}
/* Handle receive interrupt */
count = Chip_UART_Read(LPC_USART, &g_uCOM.rxBuf[g_uCOM.rxBuf_uartIndex], UCOM_BUF_SZ - g_uCOM.rxBuf_uartIndex);
if (count) {
/* Note, following logic works if UCOM_BUF_SZ is 2^n size only. */
g_uCOM.rxBuf_uartIndex = (g_uCOM.rxBuf_uartIndex + count) & (UCOM_BUF_SZ - 1);
/* If USB Tx is not busy kick start USB Tx */
if (g_uCOM.usbTxBusy == 0) {
g_uCOM.usbTxBusy = 1;
count = USBD_API->hw->WriteEP(g_uCOM.hUsb, USB_CDC_IN_EP, &g_uCOM.rxBuf[g_uCOM.rxBuf_usbIndex], count);
g_uCOM.rxBuf_usbIndex = (g_uCOM.rxBuf_usbIndex + count) & (UCOM_BUF_SZ - 1);
}
}
}
void UART_IRQHandler(UCOM_DATA_T *pUcom )
{
uint32_t count = 0;
/* Handle transmit interrupt if enabled */
if (pUcom->selected->IER & UART_IER_THREINT) {
if (pUcom->txBuf_count > 0) {
count = Chip_UART_Send(pUcom->selected, &pUcom->txBuf[pUcom->txBuf_uartIndex], pUcom->txBuf_count);
pUcom->txBuf_count -= count;
pUcom->txBuf_uartIndex += count;
}
/* If usbRxBuf empty check if any packet pending USB EP RAM */
if (pUcom->txBuf_count < 1) {
if ((pUcom->usbRxPending > 0) && USB_IsConfigured(pUcom->hUsb)) {
pUcom->usbRxPending--;
pUcom->txBuf_count = USBD_API->hw->ReadEP(pUcom->hUsb, pUcom->outEndpoint, pUcom->txBuf);
pUcom->txBuf_uartIndex = 0;
}
else {
/* all data transmitted on UART disable UART_IER_THREINT */
Chip_UART_IntDisable(pUcom->selected, UART_IER_THREINT);
}
}
}
/* Handle receive interrupt */
count = Chip_UART_Read(pUcom->selected, &pUcom->rxBuf[pUcom->rxBuf_uartIndex], UCOM_BUF_SZ - pUcom->rxBuf_uartIndex);
if (count) {
/* Note, following logic works if UCOM_BUF_SZ is 2^n size only. */
pUcom->rxBuf_uartIndex = (pUcom->rxBuf_uartIndex + count) & (UCOM_BUF_SZ - 1);
/* If USB Tx is not busy kick start USB Tx */
if ((pUcom->usbTxBusy == 0) && USB_IsConfigured(pUcom->hUsb)) {
pUcom->usbTxBusy = 1;
count = USBD_API->hw->WriteEP(pUcom->hUsb, pUcom->inEndpoint, &pUcom->rxBuf[pUcom->rxBuf_usbIndex], count);
pUcom->rxBuf_usbIndex = (pUcom->rxBuf_usbIndex + count) & (UCOM_BUF_SZ - 1);
}
}
}
extern int32_t ciaaDriverUart_close(ciaaDevices_deviceType const * const device)
{
/* disable tx and rx interrupt */
Chip_UART_IntDisable((LPC_USART_T *)device->loLayer, UART_IER_THREINT | UART_IER_RBRINT);
return 0;
}
/**
* @brief Main UART program body
* @return Always returns 1
*/
int main(void)
{
uint8_t key;
int bytes;
SystemCoreClockUpdate();
Board_Init();
Init_UART_PinMux();
Board_LED_Set(0, false);
/* Before setting up the UART, the global UART clock for USARTS 1-4
must first be setup. This requires setting the UART divider and
the UART base clock rate to 16x the maximum UART rate for all
UARTs. */
#if defined(USE_INTEGER_CLOCK)
/* Use main clock rate as base for UART baud rate divider */
Chip_Clock_SetUARTBaseClockRate(Chip_Clock_GetMainClockRate(), false);
#else
/* Use 128x expected UART baud rate for fractional baud mode. */
Chip_Clock_SetUARTBaseClockRate((115200 * 128), true);
#endif
/* Setup UART */
Chip_UART_Init(LPC_USART);
Chip_UART_ConfigData(LPC_USART, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1);
Chip_UART_SetBaud(LPC_USART, UART_TEST_DEFAULT_BAUDRATE);
/* Optional for low clock rates only: Chip_UART_SetBaudWithRTC32K(LPC_USART, 300); */
Chip_UART_Enable(LPC_USART);
Chip_UART_TXEnable(LPC_USART);
/* Before using the ring buffers, initialize them using the ring
buffer init function */
RingBuffer_Init(&rxring, rxbuff, 1, UART_RB_SIZE);
RingBuffer_Init(&txring, txbuff, 1, UART_RB_SIZE);
/* Enable receive data and line status interrupt */
Chip_UART_IntEnable(LPC_USART, UART_INTEN_RXRDY);
Chip_UART_IntDisable(LPC_USART, UART_INTEN_TXRDY); /* May not be needed */
/* Enable UART interrupt */
NVIC_EnableIRQ(LPC_IRQNUM);
/* Initial message sent using blocking method to prevent ring
buffer overflow */
Chip_UART_SendBlocking(LPC_USART, inst1, sizeof(inst1) - 1);
Chip_UART_SendRB(LPC_USART, &txring, inst2, sizeof(inst2) - 1);
/* Poll the receive ring buffer for the ESC (ASCII 27) key */
key = 0;
while (key != 27) {
bytes = Chip_UART_ReadRB(LPC_USART, &rxring, &key, 1);
if (bytes > 0) {
/* Wrap value back around */
if (Chip_UART_SendRB(LPC_USART, &txring, (const uint8_t *) &key, 1) != 1) {
Board_LED_Toggle(0);/* Toggle LED if the TX FIFO is full */
}
}
}
/* DeInitialize UART peripheral */
NVIC_DisableIRQ(LPC_IRQNUM);
Chip_UART_DeInit(LPC_USART);
return 1;
}
