//------------------------------------------------------------------------
// ContainCheckStoreIndir: determine whether the sources of a STOREIND node should be contained.
//
// Arguments:
// node - pointer to the node
//
void Lowering::ContainCheckStoreIndir(GenTreeIndir* node)
{
#ifdef _TARGET_ARM64_
GenTree* src = node->gtOp.gtOp2;
if (!varTypeIsFloating(src->TypeGet()) && src->IsIntegralConst(0))
{
// an integer zero for 'src' can be contained.
MakeSrcContained(node, src);
}
#endif // _TARGET_ARM64_
ContainCheckIndir(node);
}
//------------------------------------------------------------------------
// TreeNodeInfoInitIndir: Specify register requirements for address expression
// of an indirection operation.
//
// Arguments:
// indirTree - GT_IND, GT_STOREIND, block node or GT_NULLCHECK gentree node
//
void Lowering::TreeNodeInfoInitIndir(GenTreeIndir* indirTree)
{
ContainCheckIndir(indirTree);
// If this is the rhs of a block copy (i.e. non-enregisterable struct),
// it has no register requirements.
if (indirTree->TypeGet() == TYP_STRUCT)
{
return;
}
TreeNodeInfo* info = &(indirTree->gtLsraInfo);
bool isStore = (indirTree->gtOper == GT_STOREIND);
info->srcCount = GetIndirSourceCount(indirTree);
GenTree* addr = indirTree->Addr();
GenTree* index = nullptr;
unsigned cns = 0;
#ifdef _TARGET_ARM_
// Unaligned loads/stores for floating point values must first be loaded into integer register(s)
if (indirTree->gtFlags & GTF_IND_UNALIGNED)
{
var_types type = TYP_UNDEF;
if (indirTree->OperGet() == GT_STOREIND)
{
type = indirTree->AsStoreInd()->Data()->TypeGet();
}
else if (indirTree->OperGet() == GT_IND)
{
type = indirTree->TypeGet();
}
if (type == TYP_FLOAT)
{
info->internalIntCount = 1;
}
else if (type == TYP_DOUBLE)
{
info->internalIntCount = 2;
}
}
#endif
if (addr->isContained())
{
assert(addr->OperGet() == GT_LEA);
GenTreeAddrMode* lea = addr->AsAddrMode();
index = lea->Index();
cns = lea->gtOffset;
// On ARM we may need a single internal register
// (when both conditions are true then we still only need a single internal register)
if ((index != nullptr) && (cns != 0))
{
// ARM does not support both Index and offset so we need an internal register
info->internalIntCount++;
}
else if (!emitter::emitIns_valid_imm_for_ldst_offset(cns, emitTypeSize(indirTree)))
{
// This offset can't be contained in the ldr/str instruction, so we need an internal register
info->internalIntCount++;
}
}
}