/*!
* ======== InterruptDucati_intSend ========
* Send interrupt to the remote processor
*/
Void InterruptDucati_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo,
UArg arg)
{
UInt key;
if (remoteProcId == InterruptDucati_videoProcId ||
remoteProcId == InterruptDucati_vpssProcId) {
if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
/* VPSS-M3 to VIDEO-M3 */
REG16(INTERRUPT_VIDEO) |= 0x1;
}
else {
/* VIDEO-M3 to VPSS-M3 */
REG16(INTERRUPT_VPSS) |= 0x1;
}
}
else if (remoteProcId == InterruptDucati_dspProcId) {
if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
/* VPSS-M3 to DSP */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(VPSS_TO_DSP)) == 0) {
REG32(MAILBOX_MESSAGE(VPSS_TO_DSP)) = arg;
}
Hwi_restore(key);
}
else {
/* VIDEO-M3 to DSP */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(VIDEO_TO_DSP)) == 0) {
REG32(MAILBOX_MESSAGE(VIDEO_TO_DSP)) = arg;
}
Hwi_restore(key);
}
}
else { /* HOSTINT */
if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
/* VPSS-M3 to HOST */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(VPSS_TO_HOST)) == 0) {
REG32(MAILBOX_MESSAGE(VPSS_TO_HOST)) = arg;
}
Hwi_restore(key);
}
else {
/* VIDEO-M3 to HOST */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(VIDEO_TO_HOST)) == 0) {
REG32(MAILBOX_MESSAGE(VIDEO_TO_HOST)) = arg;
}
Hwi_restore(key);
}
}
}
/*!
* ======== InterruptDucati_intPost ========
* Simulate an interrupt from a remote processor
*/
Void InterruptDucati_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo,
UArg arg)
{
UInt key;
if (srcProcId == InterruptDucati_videoProcId ||
srcProcId == InterruptDucati_vpssProcId) {
if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
/* VIDEO-M3 to VPSS-M3 */
REG16(INTERRUPT_VPSS) |= 0x1;
}
else {
/* VPSS-M3 to VIDEO-M3 */
REG16(INTERRUPT_VIDEO) |= 0x1;
}
}
else if (srcProcId == InterruptDucati_dspProcId) {
if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
/* DSP to VPSS-M3 */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(DSP_TO_VPSS)) == 0) {
REG32(MAILBOX_MESSAGE(DSP_TO_VPSS)) = arg;
}
Hwi_restore(key);
}
else {
/* DSP to VIDEO-M3 */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(DSP_TO_VIDEO)) == 0) {
REG32(MAILBOX_MESSAGE(DSP_TO_VIDEO)) = arg;
}
Hwi_restore(key);
}
}
else { /* HOSTINT */
if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
/* HOST to VPSS-M3 */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(HOST_TO_VPSS)) == 0) {
REG32(MAILBOX_MESSAGE(HOST_TO_VPSS)) = arg;
}
Hwi_restore(key);
}
else {
/* HOST to VIDEO-M3 */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(HOST_TO_VIDEO)) == 0) {
REG32(MAILBOX_MESSAGE(HOST_TO_VIDEO)) = arg;
}
Hwi_restore(key);
}
}
}
/*!
* ======== InterruptDucati_intClear ========
* Clear interrupt
*/
UInt InterruptDucati_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
if (remoteProcId == InterruptDucati_videoProcId ||
remoteProcId == InterruptDucati_vpssProcId) {
arg = REG32(InterruptDucati_ducatiCtrlBaseAddr);
/* Look at BIOS's ducati Core id */
if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
if ((REG16(INTERRUPT_VIDEO) & 0x1) == 0x1) {
/* VPSS-M3 to VIDEO-M3 */
REG16(INTERRUPT_VIDEO) &= ~(0x1);
}
}
else {
if ((REG16(INTERRUPT_VPSS) & 0x1) == 0x1) {
/* VIDEO-M3 to VPSS-M3 */
REG16(INTERRUPT_VPSS) &= ~(0x1);
}
}
}
else if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
if (remoteProcId == InterruptDucati_hostProcId) {
/* HOST to VIDEO-M3 */
arg = REG32(MAILBOX_MESSAGE(HOST_TO_VIDEO));
REG32(MAILBOX_IRQSTATUS_CLR_VIDEO) = MAILBOX_REG_VAL(HOST_TO_VIDEO);
}
else {
/* DSP to VIDEO-M3 */
arg = REG32(MAILBOX_MESSAGE(DSP_TO_VIDEO));
REG32(MAILBOX_IRQSTATUS_CLR_VIDEO) = MAILBOX_REG_VAL(DSP_TO_VIDEO);
}
}
else { /* M3DSSINT */
if (remoteProcId == InterruptDucati_hostProcId) {
/* HOST to VPSS-M3 */
arg = REG32(MAILBOX_MESSAGE(HOST_TO_VPSS));
REG32(MAILBOX_IRQSTATUS_CLR_VPSS) = MAILBOX_REG_VAL(HOST_TO_VPSS);
}
else {
/* DSP to VPSS-M3 */
arg = REG32(MAILBOX_MESSAGE(DSP_TO_VPSS));
REG32(MAILBOX_IRQSTATUS_CLR_VPSS) = MAILBOX_REG_VAL(DSP_TO_VPSS);
}
}
return (arg);
}
/*
* ======== Core_hwiFunc ========
*/
Void Core_hwiFunc(UArg arg)
{
if (arg == Core_numCores) {
/* Scheduler interrupt */
Core_module->schedulerInts[Core_getId()] += 1;
}
else {
if (Core_module->ipcMsg[arg].func) {
Core_module->ipcMsg[arg].func(Core_module->ipcMsg[arg].arg);
}
/* Signal operation complete */
Core_module->syncCores[arg][Core_getId()] = TRUE;
}
}
/*!
* ======== InterruptDucati_intShmMbxStub ========
*/
Void InterruptDucati_intShmMbxStub(UArg arg)
{
InterruptDucati_FxnTable *table;
if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
if ((REG32(MAILBOX_IRQENABLE_SET_VIDEO) &
MAILBOX_REG_VAL(DSP_TO_VIDEO)) &&
REG32(MAILBOX_STATUS(DSP_TO_VIDEO)) != 0) { /* DSP to VIDEO-M3 */
table = &(InterruptDucati_module->fxnTable[0]);
(table->func)(table->arg);
}
if ((REG32(MAILBOX_IRQENABLE_SET_VIDEO) &
MAILBOX_REG_VAL(HOST_TO_VIDEO)) &&
REG32(MAILBOX_STATUS(HOST_TO_VIDEO)) != 0) { /* HOST to VIDEO-M3 */
table = &(InterruptDucati_module->fxnTable[1]);
(table->func)(table->arg);
}
}
else {
if ((REG32(MAILBOX_IRQENABLE_SET_VPSS) &
MAILBOX_REG_VAL(DSP_TO_VPSS)) &&
REG32(MAILBOX_STATUS(DSP_TO_VPSS)) != 0) { /* DSP to VPSS-M3 */
table = &(InterruptDucati_module->fxnTable[0]);
(table->func)(table->arg);
}
if ((REG32(MAILBOX_IRQENABLE_SET_VPSS) &
MAILBOX_REG_VAL(HOST_TO_VPSS)) &&
REG32(MAILBOX_STATUS(HOST_TO_VPSS)) != 0) { /* HOST to VPSS-M3 */
table = &(InterruptDucati_module->fxnTable[1]);
(table->func)(table->arg);
}
}
}
/*
* ======== Swi_restore ========
*/
Void Swi_restore(UInt swiKey)
{
if (swiKey == FALSE) {
if (Core_getId() != 0) {
Swi_restoreSMP();
return;
}
Core_hwiDisable();
if (Swi_module->curSet) {
Hwi_enable();
Swi_schedule(); /* sets locked to FALSE */
}
else {
Swi_module->locked = FALSE;
if (BIOS_taskEnabled) {
TASK_RESTORE(TASK_DISABLE()); /* required for Swi's posted from Tasks */
}
else {
Hwi_enable();
}
}
}
}
/*
* ======== Core_notify ========
*/
Void Core_notify(Core_IpcFuncPtr func, UArg arg, UInt mask)
{
UInt idx, coreId;
/* Store function ptr, argument and sync flag in msg buffer */
coreId = Core_getId();
Core_module->ipcMsg[coreId].func = func;
Core_module->ipcMsg[coreId].arg = arg;
/* Init syncCores flag */
for (idx = 0; idx < Core_numCores; idx++) {
Core_module->syncCores[coreId][idx] = FALSE;
}
/* Interrupt other cores */
Hwi_raiseSGI(mask, coreId);
/* Wait for all other cores */
for (idx = 0; idx < Core_numCores; idx++) {
if ((idx != coreId) && (mask & (0x1 << idx))) {
while (!(Core_module->syncCores[coreId][idx]));
Core_module->syncCores[coreId][idx] = FALSE;
}
}
}
/*
* ======== IpcPower_hibernateUnlock ========
*/
UInt IpcPower_hibernateUnlock()
{
IArg hwiKey;
#ifndef SMP
UInt coreIdx = Core_getId();
#endif
hwiKey = Hwi_disable();
#ifndef SMP
if (IpcPower_hibLocks[coreIdx] > 0) {
IpcPower_hibLocks[coreIdx] -= 1;
}
#else
if (IpcPower_hibLocks > 0) {
IpcPower_hibLocks--;
}
#endif
Hwi_restore(hwiKey);
#ifndef SMP
return (IpcPower_hibLocks[coreIdx]);
#else
return (IpcPower_hibLocks);
#endif
}
/*
* ======== Core_syncStartup ========
*/
Void Core_syncStartup()
{
volatile UInt32 dummy;
UInt8 coreId = Core_getId();
if (coreId != 0) {
/* Write to word1 to signal init complete */
REG32(IMMWORD1) = 0xAAAAAAAA;
/* Perform a dummy read to ensure register write completed */
dummy = REG32(IMMWORD1);
}
else {
/* Enable IMM (keep error handling disabled) */
REG32(IMMGCTRL) = IMM_ERROR_INTERRUPT_DISABLE |
IMM_ERROR_OVERWRITE_DISABLE;
/* Write to word0 to signal init complete */
REG32(IMMWORD0) = 0x55555555;
/* Wait for Core1 to signal initialization complete */
while (!(REG32(IMMFLAG) & IMM_MESSAGE_WORD1));
/* Clear the flag for word1 */
REG32(IMMFLAG) = 0x2;
/* Disable IMM */
REG32(IMMGCTRL) = IMM_RESET_VALUE;
/* Perform a dummy read to ensure register write completed */
dummy = REG32(IMMGCTRL);
}
}
/*!
* ======== InterruptDucati_intDisable ========
* Disables remote processor interrupt
*/
Void InterruptDucati_intDisable(UInt16 remoteProcId,
IInterrupt_IntInfo *intInfo)
{
/*
* If the remote processor communicates via mailboxes, we should disable
* the Mailbox IRQ instead of disabling the Hwi because multiple mailboxes
* share the same Hwi
*/
if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
if (remoteProcId == InterruptDucati_hostProcId) {
REG32(MAILBOX_IRQENABLE_CLR_VIDEO) = MAILBOX_REG_VAL(HOST_TO_VIDEO);
}
else if (remoteProcId == InterruptDucati_dspProcId) {
REG32(MAILBOX_IRQENABLE_CLR_VIDEO) = MAILBOX_REG_VAL(DSP_TO_VIDEO);
}
else {
Hwi_disableInterrupt(M3INT);
}
}
else {
if (remoteProcId == InterruptDucati_hostProcId) {
REG32(MAILBOX_IRQENABLE_CLR_VPSS) = MAILBOX_REG_VAL(HOST_TO_VPSS);
}
else if (remoteProcId == InterruptDucati_dspProcId) {
REG32(MAILBOX_IRQENABLE_CLR_VPSS) = MAILBOX_REG_VAL(DSP_TO_VPSS);
}
else {
Hwi_disableInterrupt(M3INT);
}
}
}
/*!
* ======== BIOS_getThreadType ========
*/
BIOS_ThreadType BIOS_getThreadType(Void)
{
if (BIOS_smpEnabled == TRUE) {
return (BIOS_module->smpThreadType[Core_getId()]);
}
else {
return (BIOS_module->threadType);
}
}
/*
* ======== Core_startup ========
* Other core's intial thread.
* Executes on stack provided by Core module.
*/
Void Core_startup()
{
/* Init Cache and MMU */
Cache_startup();
/* Install vector table */
Hwi_init();
/* Init exception regs */
Exception_initCoreX();
/*
* Initialize GIC CPU Interface and FIQ stack
*
* Note: GIC Distributor will be initialized by core 0
*/
Hwi_initIntControllerCoreX();
/* Initialize this core's Hwi stack to enable stack checking */
if (Core_initStackFlag) {
ti_sysbios_hal_Hwi_initStack();
}
/* Signal to core 0 that this core's startup routine is complete */
Core_module->syncCores[0][Core_getId()] = TRUE;
/* Wait for store to complete */
__asm__ __volatile__ (
"dmb ish"
);
/* Wait for core 0's signal to start running tasks */
while(!Core_module->syncCores[0][0]);
/*
* Enable FIQ interrupts on this core. Task_startCore() will
* enable IRQs.
*/
if (Hwi_enableSecureMode) {
Hwi_enableFIQ();
}
Task_startCore(Core_getId());
}
/*
* ======== Core_Module_startup ========
*/
Int Core_Module_startup(Int status)
{
UInt8 coreId = Core_getId();
if (Core_id != coreId) {
Error_raise(NULL, Core_E_mismatchedIds, Core_id, coreId);
}
return (Startup_DONE);
}
/*
* ======== GateSmp_leave ========
*/
Void GateSmp_leave(GateSmp_Object *gate, IArg key)
{
UInt coreId;
volatile UInt8 *gateBytePtr;
coreId = Core_getId();
gateBytePtr = (volatile UInt8 *)&gate->gateWord;
gateBytePtr = &gateBytePtr[coreId];
*gateBytePtr = 0;
}
Void Core_startCore1()
{
if (Core_getId() != 0) {
return;
}
/* put C stack in the middle of core 1's Hwi stack to avoid collision */
*(Char **)(0x0008) = &Core_module->core1HwiStack[Core_core1HwiStackSize/2];
*(UInt32 *)(0x000C) = (UInt32)Core_core1Startup;
}
/*
* ======== Core_lock ========
*/
Void Core_lock()
{
UInt coreId;
coreId = Core_getId();
if (!(Core_module->gateEntered[coreId])) {
GateSmp_enter(Core_gate);
Core_module->gateEntered[coreId] = TRUE;
}
}
/*
* ======== Swi_post ========
*/
Void Swi_post(Swi_Object *swi)
{
UInt hwiKey;
UInt swiKey;
#ifndef ti_sysbios_knl_Swi_DISABLE_ALL_HOOKS
Int i;
#endif
Log_write3(Swi_LM_post, (UArg)swi, (UArg)swi->fxn, (UArg)swi->priority);
hwiKey = Hwi_disable();
if (swi->posted) {
Hwi_restore(hwiKey);
return;
}
swi->posted = TRUE;
swiKey = Swi_disable();
/* Place the Swi in the appropriate ready Queue. */
Queue_enqueue(swi->readyQ, (Queue_Elem *)swi);
/* Add this priority to current set */
Swi_module->curSet |= swi->mask;
Hwi_restore(hwiKey); /* Not in FIFO order. OK! */
#ifndef ti_sysbios_knl_Swi_DISABLE_ALL_HOOKS
/*
* This hook location supports the STS "set ready time" operation on
* Swis. This is equivalent to pre-BIOS 6.
*/
for (i = 0; i < Swi_hooks.length; i++) {
if (Swi_hooks.elem[i].readyFxn != NULL) {
Swi_hooks.elem[i].readyFxn(swi);
}
}
#endif
/*
* Modified Swi_restore().
* No need to check curSet since we just set it.
*/
if (swiKey == FALSE) {
if (Core_getId() == 0) {
Swi_schedule(); /* unlocks Swi scheduler on return */
}
else {
Swi_restoreSMP(); /* interrupt core 0 to do the work */
}
}
}
/*
* ======== Exception_excDumpContext ========
*/
Void Exception_excDumpContext(UInt pc)
{
Exception_ExcContext *excp;
Char *ttype;
UInt coreId = 0;
#if (ti_sysbios_BIOS_smpEnabled__D)
coreId = Core_getId();
#endif
excp = Exception_module->excContext[coreId];
switch (excp->threadType) {
case BIOS_ThreadType_Task: {
ttype = "Task";
break;
}
case BIOS_ThreadType_Swi: {
ttype = "Swi";
break;
}
case BIOS_ThreadType_Hwi: {
ttype = "Hwi";
break;
}
case BIOS_ThreadType_Main: {
ttype = "Main";
break;
}
}
System_printf("Exception occurred in ThreadType_%s.\n", ttype);
System_printf("%s handle: 0x%x.\n", ttype, excp->threadHandle);
System_printf("%s stack base: 0x%x.\n", ttype, excp->threadStack);
System_printf("%s stack size: 0x%x.\n", ttype, excp->threadStackSize);
System_printf ("R0 = 0x%08x R8 = 0x%08x\n", excp->r0, excp->r8);
System_printf ("R1 = 0x%08x R9 = 0x%08x\n", excp->r1, excp->r9);
System_printf ("R2 = 0x%08x R10 = 0x%08x\n", excp->r2, excp->r10);
System_printf ("R3 = 0x%08x R11 = 0x%08x\n", excp->r3, excp->r11);
System_printf ("R4 = 0x%08x R12 = 0x%08x\n", excp->r4, excp->r12);
System_printf ("R5 = 0x%08x SP(R13) = 0x%08x\n", excp->r5, excp->sp);
System_printf ("R6 = 0x%08x LR(R14) = 0x%08x\n", excp->r6, excp->lr);
System_printf ("R7 = 0x%08x PC(R15) = 0x%08x\n", excp->r7, excp->pc);
System_printf ("PSR = 0x%08x\n", excp->psr);
System_printf ("DFSR = 0x%08x IFSR = 0x%08x\n", excp->dfsr, excp->ifsr);
#ifdef __TI_ARM_V5__
System_printf ("DFAR = 0x%08x\n", excp->dfar);
#else
System_printf ("DFAR = 0x%08x IFAR = 0x%08x\n", excp->dfar, excp->ifar);
#endif
}
/*
* ======== SysMin_putch ========
*/
Void SysMin_putch(Char ch)
{
UInt coreId;
UInt outidx;
UInt i;
Char *outbuf;
IArg key;
if (SysMin_bufSize != 0) {
/*
* only disable local interrupts to place chars in
* local line buffer
*/
key = (IArg)Core_hwiDisable();
coreId = Core_getId();
outidx = module->lineBuffers[coreId].outidx;
outbuf = module->lineBuffers[coreId].outbuf;
outbuf[outidx++] = ch;
SysMin_module->lineBuffers[coreId].outidx = outidx;
/* At EOL, copy core's line buffer to shared outbuf */
if ((ch == '\n') || (outidx >= 256)) {
/*
* disable interrupts globally to transfer lines
* to the shared output buffer
*/
Gate_enterSystem();
for (i = 0; i < outidx; i++) {
module->outbuf[module->outidx++] = outbuf[i];
if (module->outidx == SysMin_bufSize) {
module->outidx = 0;
module->wrapped = TRUE;
}
}
SysMin_module->lineBuffers[coreId].outidx = 0;
Gate_leaveSystem(key);
}
else {
/* restore local interrupts */
Core_hwiRestore((UInt)key);
}
}
}
/*!
* ======== InterruptM3_intDisable ========
* Disables remote processor interrupt
*/
Void InterruptM3_intDisable()
{
/*
* If the remote processor communicates via mailboxes, we should disable
* the Mailbox IRQ instead of disabling the Hwi because multiple mailboxes
* share the same Hwi
*/
if (Core_getId() == 0) {
REG32(MAILBOX_IRQENABLE_CLR_M3) = MAILBOX_REG_VAL(SYSM3_MBX);
}
else {
Hwi_disableInterrupt(M3INT);
}
}
/*
* ======== Core_atexit ========
*/
Void Core_atexit(Int arg)
{
UInt key;
UInt coreId = Core_getId();
Task_unlockSched();
Swi_unlockSched();
Core_unlock();
/* force other cores to exit */
key = Core_notifySpinLock();
Core_notify(&Core_exit, (UArg)coreId, (Core_CPUMASK ^ (0x1 << coreId)));
Core_notifySpinUnlock(key);
}
/*
* ======== Watchdog_idleBegin ========
*/
Void Watchdog_idleBegin(Void)
{
Int core = 0;
#ifdef SMP
core = Core_getId();
if (core != 0) {
Watchdog_stop(core);
}
else
#endif
{
Watchdog_kick(core);
}
}
/*
* ======== Watchdog_swiPrehook ========
*/
Void Watchdog_swiPrehook(Swi_Handle swi)
{
Int core = 0;
#ifdef SMP
core = Core_getId();
if (core != 0) {
Watchdog_start(core);
}
else
#endif
{
Watchdog_kick(core);
}
}
/*
* ======== Watchdog_taskSwitch ========
* Refresh/restart watchdog timer whenever task switch scheduling happens
*/
Void Watchdog_taskSwitch(Task_Handle p, Task_Handle n)
{
Int core = 0;
#ifdef SMP
core = Core_getId();
if (core != 0) {
Watchdog_start(core);
}
else
#endif
{
Watchdog_kick(core);
}
}
/*!
* ======== BIOS_setThreadType ========
*/
BIOS_ThreadType BIOS_setThreadType(BIOS_ThreadType ttype)
{
BIOS_ThreadType prevThreadType;
if (BIOS_smpEnabled == TRUE) {
UInt coreId = Core_getId();
prevThreadType = BIOS_module->smpThreadType[coreId];
BIOS_module->smpThreadType[coreId] = ttype;
}
else {
prevThreadType = BIOS_module->threadType;
BIOS_module->threadType = ttype;
}
return (prevThreadType);
}
/*
* ======== Core_exit ========
*/
Void Core_exit(UArg arg)
{
Task_unlockSched();
Swi_unlockSched();
Core_unlock();
/* Signal operation complete */
Core_module->syncCores[arg][Core_getId()] = TRUE;
/*
* Call _exit() instead of abort. abort() internally
* calls raise() which will invoke ReentSupport_getReent()
* from a Hwi context and cause an assertion failure.
*/
_exit(0);
}
/*
* ======== Core_hwiFunc ========
*/
Void Core_hwiFunc(UArg arg)
{
UInt coreId = Core_getId();
Core_module->schedulerInts[coreId] += 1;
if (Core_module->exitFlag == TRUE) {
Core_module->exitFlag = FALSE;
Task_unlockSched();
Swi_unlockSched();
Core_unlock();
abort();
}
if (coreId == 0) {
Hwi_flushVnvic();
}
}
/*
* ======== GateSmp_enter ========
*/
IArg GateSmp_enter(GateSmp_Object *gate)
{
UInt stalls = 0;
UInt coreId = Core_getId();
volatile UInt8 *gateBytePtr;
gateBytePtr = (volatile UInt8 *)&gate->gateWord;
gateBytePtr = &gateBytePtr[coreId];
while (TRUE) {
*gateBytePtr = 1;
if (gate->gateWord > 0x100) {
*gateBytePtr = 0;
/* make core 1's loop a little slower to avoid a stalemate */
if (coreId == 1) {
*gateBytePtr = *gateBytePtr;
*gateBytePtr = *gateBytePtr;
*gateBytePtr = *gateBytePtr;
}
if (GateSmp_enableStats == TRUE) {
stalls += 1;
}
}
else {
if (GateSmp_enableStats == TRUE) {
if (stalls) {
gate->stalls += 1;
gate->totalStalls += stalls;
if (stalls > gate->maxStall) {
gate->maxStall = stalls;
}
}
else {
gate->noStalls += 1;
}
}
Assert_isTrue((*gateBytePtr == 1), NULL);
return (0);
}
}
}
/*
* ======== Core_atexit ========
*/
Void Core_atexit(Int arg)
{
if ((Core_module->exitFlag == TRUE) || (Core_syncExits == FALSE)) {
Core_module->exitFlag = FALSE;
Task_unlockSched();
Swi_unlockSched();
Core_unlock();
return;
}
Core_module->exitFlag = TRUE;
Task_unlockSched();
Swi_unlockSched();
Core_unlock();
/* interrupt the other core */
Core_interruptCore(Core_getId() ^ 1);
while (Core_module->exitFlag);
}
/*
* ======== Core_unlock ========
*/
Void Core_unlock()
{
UInt hwiKey, coreId;
/* Hwi_disable() */
hwiKey = _set_interrupt_priority(Hwi_disablePriority);
coreId = Core_getId();
// TODO Check BIOS.swiEnabled and BIOS.taskEnabled before using
// Task_enabled() and Swi_enabled() APIs.
if (Core_module->gateEntered[coreId]) {
if (Task_enabled() && Swi_enabled()) {
GateSmp_leave(Core_gate, 0);
Core_module->gateEntered[coreId] = FALSE;
}
}
/* Hwi_restore() */
_set_interrupt_priority(hwiKey);
}
